[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing...

[oota-llvm.git] / test / CodeGen / WebAssembly / memory-addr32.ll

diff --git a/test/CodeGen/WebAssembly/memory-addr32.ll b/test/CodeGen/WebAssembly/memory-addr32.ll
index 3cb27ffe662fe0a840e4e47ea9a620bff43e5ea4..194fd64cce82c19cfe02a40d62e4688c7975df52 100644 (file)
--- a/test/CodeGen/WebAssembly/memory-addr32.ll
+++ b/test/CodeGen/WebAssembly/memory-addr32.ll
@@ -5,20 +5,8 @@
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-declare i32 @llvm.wasm.page.size.i32() nounwind readnone
 declare i32 @llvm.wasm.memory.size.i32() nounwind readnone
-declare void @llvm.wasm.resize.memory.i32(i32) nounwind
-
-; CHECK-LABEL: page_size:
-; CHECK-NEXT: .result i32{{$}}
-; CHECK-NEXT: .local i32{{$}}
-; CHECK-NEXT: page_size
-; CHECK-NEXT: set_local 0, pop{{$}}
-; CHECK-NEXT: return (get_local 0){{$}}
-define i32 @page_size() {
-  %a = call i32 @llvm.wasm.page.size.i32()
-  ret i32 %a
-}
+declare void @llvm.wasm.grow.memory.i32(i32) nounwind
 
 ; CHECK-LABEL: memory_size:
 ; CHECK-NEXT: .result i32{{$}}
@@ -31,12 +19,12 @@ define i32 @memory_size() {
   ret i32 %a
 }
 
-; CHECK-LABEL: resize_memory:
+; CHECK-LABEL: grow_memory:
 ; CHECK-NEXT: .param i32
 ; CHECK-NEXT: .local i32{{$}}
-; CHECK: resize_memory (get_local 1)
+; CHECK: grow_memory (get_local 1)
 ; CHECK-NEXT: return
-define void @resize_memory(i32 %n) {
-  call void @llvm.wasm.resize.memory.i32(i32 %n)
+define void @grow_memory(i32 %n) {
+  call void @llvm.wasm.grow.memory.i32(i32 %n)
   ret void
 }