Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / X86 / 2007-10-12-CoalesceExtSubReg.ll

diff --git a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
index 99b863ee21491aa8536722f15a397e0f5bbe6c6e..8091bd1bc1ca042b2ad4ae2c06183d2fc503ed68 100644 (file)
--- a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | not movb
+; RUN: llc < %s -march=x86 | not grep movb
 
-define i16 @f(i32* %bp, i32* %ss) signext  {
+define signext i16 @f(i32* %bp, i32* %ss)   {
 entry:
        br label %cond_next127
 
@@ -9,10 +9,7 @@ cond_next127:          ; preds = %cond_next391, %entry
        %tmp149 = mul i32 0, %v.1               ; <i32> [#uses=0]
        %tmp254 = and i32 0, 15         ; <i32> [#uses=1]
        %tmp256 = and i32 0, 15         ; <i32> [#uses=2]
-       br i1 false, label %cond_true267, label %cond_next391
-
-cond_true267:          ; preds = %cond_next127
-       ret i16 0
+       br label %cond_next391
 
 cond_next391:          ; preds = %cond_next127
        %tmp393 = load i32* %ss, align 4                ; <i32> [#uses=1]