Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / 2007-11-06-InstrSched.ll

diff --git a/test/CodeGen/X86/2007-11-06-InstrSched.ll b/test/CodeGen/X86/2007-11-06-InstrSched.ll
index 605fb551205b2b2903fd3f8dc8e3c25e9bc43df9..838a0c35646f5531d14af0368a6377b919e3a58e 100644 (file)
--- a/test/CodeGen/X86/2007-11-06-InstrSched.ll
+++ b/test/CodeGen/X86/2007-11-06-InstrSched.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep lea
+; RUN: llc < %s -march=x86 -mcpu=generic -mattr=+sse2 | not grep lea
 
 define float @foo(i32* %x, float* %y, i32 %c) nounwind {
 entry:
@@ -13,8 +13,8 @@ bb18:         ; preds = %bb18, %entry
        %tmp45 = sitofp i32 %tmp4 to float              ; <float> [#uses=1]
        %tmp8 = getelementptr float* %y, i32 %i.0.reg2mem.0             ; <float*> [#uses=1]
        %tmp9 = load float* %tmp8, align 4              ; <float> [#uses=1]
-       %tmp11 = mul float %tmp9, %tmp45                ; <float> [#uses=1]
-       %tmp14 = add float %tmp11, %res.0.reg2mem.0             ; <float> [#uses=2]
+       %tmp11 = fmul float %tmp9, %tmp45               ; <float> [#uses=1]
+       %tmp14 = fadd float %tmp11, %res.0.reg2mem.0            ; <float> [#uses=2]
        %tmp17 = add i32 %i.0.reg2mem.0, 1              ; <i32> [#uses=2]
        %tmp21 = icmp ult i32 %tmp17, %c                ; <i1> [#uses=1]
        br i1 %tmp21, label %bb18, label %bb23