CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / 2008-09-18-inline-asm-2.ll

diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
index dfd165cc03e657fd752bb5184fac8d259ecaea26..0058d979a2fa053bd95a559cb78180179196fa68 100644 (file)
--- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -1,7 +1,6 @@
-; RUN: llc < %s -march=x86 -regalloc=linearscan | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=fast       | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=basic      | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=greedy     | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-as      | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-as     | FileCheck %s
 
 ; The 1st, 2nd, 3rd and 5th registers must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
@@ -18,7 +17,7 @@
 ; CHECK-NOT: [[A3]]
 ; CHECK: 5th=[[A5:%...]]
 ; CHECK-NOT: [[A1]]
-; CHECK-NOT; [[A5]]
+; CHECK-NOT: [[A5]]
 ; CHECK: =4th
 
 ; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.
@@ -33,12 +32,12 @@ target triple = "i386-apple-darwin8"
 
 define i32 @get(%struct.foo* %c, i8* %state) nounwind {
 entry:
-       %0 = getelementptr %struct.foo* %c, i32 0, i32 0                ; <i32*> [#uses=2]
-       %1 = getelementptr %struct.foo* %c, i32 0, i32 1                ; <i32*> [#uses=2]
-       %2 = getelementptr %struct.foo* %c, i32 0, i32 2                ; <i8**> [#uses=2]
-       %3 = load i32* %0, align 4              ; <i32> [#uses=1]
-       %4 = load i32* %1, align 4              ; <i32> [#uses=1]
-       %5 = load i8* %state, align 1           ; <i8> [#uses=1]
+       %0 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 0           ; <i32*> [#uses=2]
+       %1 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 1           ; <i32*> [#uses=2]
+       %2 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 2           ; <i8**> [#uses=2]
+       %3 = load i32, i32* %0, align 4         ; <i32> [#uses=1]
+       %4 = load i32, i32* %1, align 4         ; <i32> [#uses=1]
+       %5 = load i8, i8* %state, align 1               ; <i8> [#uses=1]
        %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind         ; <{ i32, i32, i32, i32 }> [#uses=3]
        %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0             ; <i32> [#uses=1]
        %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1            ; <i32> [#uses=1]