Fix a logic bug in x86 vector codegen: sext (zext (x) ) != sext (x) (PR20472).

[oota-llvm.git] / test / CodeGen / X86 / 2009-09-19-earlyclobber.ll

diff --git a/test/CodeGen/X86/2009-09-19-earlyclobber.ll b/test/CodeGen/X86/2009-09-19-earlyclobber.ll
index 4f44caea74c946067ba08d66c35ed0416bd7a66c..7df62fd8c37ae2d1a69ccd3e6635a57ff540280b 100644 (file)
--- a/test/CodeGen/X86/2009-09-19-earlyclobber.ll
+++ b/test/CodeGen/X86/2009-09-19-earlyclobber.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-as < %s | FileCheck %s
 ; ModuleID = '4964.c'
 ; PR 4964
 ; Registers other than RAX, RCX are OK, but they must be different.
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin10.0"
-       type { i64, i64 }               ; type %0
+       %0 = type { i64, i64 }          ; type %0
 
 define i64 @flsst(i64 %find) nounwind ssp {
 entry: