Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / atomic-or.ll

diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
index cd622908aca5dd355a7a189061f771faf905f35a..3f02eafb44a221ecb9dc7f460ae8245b6b77a0ff 100644 (file)
--- a/test/CodeGen/X86/atomic-or.ll
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -2,17 +2,27 @@
 
 ; rdar://9692967
 
-define void @do_the_sync(i64* %p, i32 %b) nounwind {
+define void @t1(i64* %p, i32 %b) nounwind {
 entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
   %tmp = load i64** %p.addr, align 8
-  call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+; CHECK: t1:
+; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
-; CHECK-NEXT: orq     $2147483648
-  %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
-  call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
+  %0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst
+  ret void
+}
+
+define void @t2(i64* %p, i32 %b) nounwind {
+entry:
+  %p.addr = alloca i64*, align 8
+  store i64* %p, i64** %p.addr, align 8
+  %tmp = load i64** %p.addr, align 8
+; CHECK: t2:
+; CHECK: lock
+; CHECK-NEXT: orq $2147483644, (%r{{.*}})
+  %0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
   ret void
 }
-declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind
-declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind