Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / X86 / atomic_op.ll

diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll
index c8cb78e34ee7194526821d397269bba46279fcfb..c5fa07d07d802cc194b48444e8e586c86e751510 100644 (file)
--- a/test/CodeGen/X86/atomic_op.ll
+++ b/test/CodeGen/X86/atomic_op.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+cmov | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 
@@ -107,10 +107,14 @@ entry:
         ; CHECK: cmpxchgl
   %17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic
        store i32 %17, i32* %old
-        ; CHECK: andl
-        ; CHECK: notl
-        ; CHECK: lock
-        ; CHECK: cmpxchgl
+        ; CHECK: movl  [[R17atomic:.*]], %eax
+        ; CHECK: movl  $1401, %[[R17mask:[a-z]*]]
+        ; CHECK: andl  %eax, %[[R17mask]]
+        ; CHECK: notl  %[[R17mask]]
+        ; CHECK: lock
+        ; CHECK: cmpxchgl      %[[R17mask]], [[R17atomic]]
+        ; CHECK: jne
+        ; CHECK: movl  %eax,
   %18 = atomicrmw nand i32* %val2, i32 1401 monotonic
   store i32 %18, i32* %old
         ; CHECK: andl