This commit enables unaligned memory accesses of vector types on AArch64 back end...

[oota-llvm.git] / test / CodeGen / X86 / avx-blend.ll

diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll
index 188efe26d92ad95c1517b12d68b1a52de382dd7b..5fcd5ff5f4c324eb762c6a0337ac3cbc4d94949b 100644 (file)
--- a/test/CodeGen/X86/avx-blend.ll
+++ b/test/CodeGen/X86/avx-blend.ll
@@ -2,26 +2,26 @@
 
 ; AVX128 tests:
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2
   ret <4 x float> %vsel
 }
 
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2
   ret <4 x i32> %vsel
 }
 
 
-;CHECK: vsel_double
-;CHECK: vblendvpd
+;CHECK-LABEL: vsel_double:
+;CHECK: vmovsd
 ;CHECK: ret
 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
   %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
@@ -29,8 +29,8 @@ define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
 }
 
 
-;CHECK: vsel_i64
-;CHECK: vblendvpd
+;CHECK-LABEL: vsel_i64:
+;CHECK: vmovsd
 ;CHECK: ret
 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
   %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
@@ -38,7 +38,7 @@ define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
 }
 
 
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
 ;CHECK: vpblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
@@ -50,7 +50,8 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
 ; AVX256 tests:
 
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float8:
+;CHECK-NOT: vinsertf128
 ;CHECK: vblendvps
 ;CHECK: ret
 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
@@ -58,15 +59,16 @@ define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
   ret <8 x float> %vsel
 }
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i328:
+;CHECK-NOT: vinsertf128
 ;CHECK: vblendvps
-;CHECK: ret
+;CHECK-NEXT: ret
 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
   %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
   ret <8 x i32> %vsel
 }
 
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double8:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
@@ -74,7 +76,7 @@ define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
   ret <8 x double> %vsel
 }
 
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i648:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
@@ -82,9 +84,18 @@ define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
   ret <8 x i64> %vsel
 }
 
+;CHECK-LABEL: vsel_double4:
+;CHECK-NOT: vinsertf128
+;CHECK: vblendvpd
+;CHECK-NEXT: ret
+define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v1, <4 x double> %v2
+  ret <4 x double> %vsel
+}
+
 ;; TEST blend + compares
-; CHECK: A
-define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
+; CHECK: testa
+define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
   ; CHECK: vcmplepd
   ; CHECK: vblendvpd
   %max_is_x = fcmp oge <2 x double> %x, %y
@@ -92,8 +103,8 @@ define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %max
 }
 
-; CHECK: B
-define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
+; CHECK: testb
+define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
   ; CHECK: vcmpnlepd
   ; CHECK: vblendvpd
   %min_is_x = fcmp ult <2 x double> %x, %y