Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / avx-cast.ll

diff --git a/test/CodeGen/X86/avx-cast.ll b/test/CodeGen/X86/avx-cast.ll
index e24cfeb50852dbdf0b2d6ebeb192fcbaa1310c5c..32d450cac9f9afd92c242fdff28ab60476896390 100644 (file)
--- a/test/CodeGen/X86/avx-cast.ll
+++ b/test/CodeGen/X86/avx-cast.ll
@@ -24,21 +24,21 @@ entry:
   ret <4 x i64> %shuffle.i
 }
 
-; CHECK: vextractf128 $0
+; CHECK-NOT: vextractf128 $0
 define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp {
 entry:
   %shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %shuffle.i
 }
 
-; CHECK: vextractf128 $0
+; CHECK-NOT: vextractf128 $0
 define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp {
 entry:
   %shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> <i32 0, i32 1>
   ret <2 x i64> %shuffle.i
 }
 
-; CHECK: vextractf128 $0
+; CHECK-NOT: vextractf128 $0
 define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp {
 entry:
   %shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> <i32 0, i32 1>