Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / avx-cvt.ll

diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll
index 6da47af5ab517bf7e2550be2ad15f415c8c12823..d0a7fe01009e03fa959af2c173b20bf0fb1f84dd 100644 (file)
--- a/test/CodeGen/X86/avx-cvt.ll
+++ b/test/CodeGen/X86/avx-cvt.ll
@@ -12,6 +12,18 @@ define <8 x i32> @fptosi00(<8 x float> %a) nounwind {
   ret <8 x i32> %b
 }
 
+; CHECK: vcvtdq2pd %xmm
+define <4 x double> @sitofp01(<4 x i32> %a) {
+  %b = sitofp <4 x i32> %a to <4 x double>
+  ret <4 x double> %b
+}
+
+; CHECK: vcvttpd2dqy %ymm
+define <4 x i32> @fptosi01(<4 x double> %a) {
+  %b = fptosi <4 x double> %a to <4 x i32>
+  ret <4 x i32> %b
+}
+
 ; CHECK: vcvtpd2psy %ymm
 ; CHECK-NEXT: vcvtpd2psy %ymm
 ; CHECK-NEXT: vinsertf128 $1
@@ -20,6 +32,12 @@ define <8 x float> @fptrunc00(<8 x double> %b) nounwind {
   ret <8 x float> %a
 }
 
+; CHECK: vcvtps2pd %xmm
+define <4 x double> @fpext00(<4 x float> %b) nounwind {
+  %a = fpext <4 x float> %b to <4 x double>
+  ret <4 x double> %a
+}
+
 ; CHECK: vcvtsi2sdq (%
 define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp {
 entry: