Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / avx-zext.ll

diff --git a/test/CodeGen/X86/avx-zext.ll b/test/CodeGen/X86/avx-zext.ll
index 795a7b3dd45c2c35ccdf114e115092db8823db93..b630e9d1461258e5f19b6436eb278f2d9e496817 100755 (executable)
--- a/test/CodeGen/X86/avx-zext.ll
+++ b/test/CodeGen/X86/avx-zext.ll
@@ -3,6 +3,7 @@
 define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
 ;CHECK: zext_8i16_to_8i32
 ;CHECK: vpunpckhwd
+;CHECK: ret
 
   %B = zext <8 x i16> %A to <8 x i32>
   ret <8 x i32>%B
@@ -11,7 +12,19 @@ define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp
 define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
 ;CHECK: zext_4i32_to_4i64
 ;CHECK: vpunpckhdq
+;CHECK: ret
 
   %B = zext <4 x i32> %A to <4 x i64>
   ret <4 x i64>%B
 }
+
+
+define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
+;CHECK: zext_8i8_to_8i32
+;CHECK: vpunpckhwd
+;CHECK: vpunpcklwd
+;CHECK: vinsertf128
+;CHECK: ret
+  %t = zext <8 x i8> %z to <8 x i32>
+  ret <8 x i32> %t
+}