CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / avx2-pmovxrm-intrinsics.ll

diff --git a/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll b/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
index 7301b7cbfc4ef0dba5072303be6b36d7ecfaffde..6bd6a5041d41bd75371e68a48cb06ee6c0f5d25a 100644 (file)
--- a/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
+++ b/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
@@ -3,7 +3,7 @@
 define <16 x i16> @test_lvm_x86_avx2_pmovsxbw(<16 x i8>* %a) {
 ; CHECK-LABEL: test_lvm_x86_avx2_pmovsxbw
 ; CHECK: vpmovsxbw (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %1)
   ret <16 x i16> %2
 }
@@ -11,7 +11,7 @@ define <16 x i16> @test_lvm_x86_avx2_pmovsxbw(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxbd
 ; CHECK: vpmovsxbd (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %1)
   ret <8 x i32> %2
 }
@@ -19,7 +19,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(<16 x i8>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxbq
 ; CHECK: vpmovsxbq (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %1)
   ret <4 x i64> %2
 }
@@ -27,7 +27,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxwd
 ; CHECK: vpmovsxwd (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %1)
   ret <8 x i32> %2
 }
@@ -35,7 +35,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxwq
 ; CHECK: vpmovsxwq (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %1)
   ret <4 x i64> %2
 }
@@ -43,7 +43,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(<4 x i32>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxdq
 ; CHECK: vpmovsxdq (%rdi), %ymm0
-  %1 = load <4 x i32>* %a, align 1
+  %1 = load <4 x i32>, <4 x i32>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %1)
   ret <4 x i64> %2
 }
@@ -51,7 +51,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(<4 x i32>* %a) {
 define <16 x i16> @test_lvm_x86_avx2_pmovzxbw(<16 x i8>* %a) {
 ; CHECK-LABEL: test_lvm_x86_avx2_pmovzxbw
 ; CHECK: vpmovzxbw (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %1)
   ret <16 x i16> %2
 }
@@ -59,7 +59,7 @@ define <16 x i16> @test_lvm_x86_avx2_pmovzxbw(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxbd
 ; CHECK: vpmovzxbd (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %1)
   ret <8 x i32> %2
 }
@@ -67,7 +67,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(<16 x i8>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxbq
 ; CHECK: vpmovzxbq (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %1)
   ret <4 x i64> %2
 }
@@ -75,7 +75,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxwd
 ; CHECK: vpmovzxwd (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %1)
   ret <8 x i32> %2
 }
@@ -83,7 +83,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxwq
 ; CHECK: vpmovzxwq (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %1)
   ret <4 x i64> %2
 }
@@ -91,7 +91,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovzxdq(<4 x i32>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxdq
 ; CHECK: vpmovzxdq (%rdi), %ymm0
-  %1 = load <4 x i32>* %a, align 1
+  %1 = load <4 x i32>, <4 x i32>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %1)
   ret <4 x i64> %2
 }