Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / crash.ll

diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll
index b5b1ad45be0c2e8c3adef49f22778d731a1b4401..35f6ec50bcb25b21cdd081fc2023efa2dc1decde 100644 (file)
--- a/test/CodeGen/X86/crash.ll
+++ b/test/CodeGen/X86/crash.ll
@@ -6,16 +6,16 @@
 ; Chain and flag folding issues.
 define i32 @test1() nounwind ssp {
 entry:
-  %tmp5.i = volatile load i32* undef              ; <i32> [#uses=1]
+  %tmp5.i = load volatile i32* undef              ; <i32> [#uses=1]
   %conv.i = zext i32 %tmp5.i to i64               ; <i64> [#uses=1]
-  %tmp12.i = volatile load i32* undef             ; <i32> [#uses=1]
+  %tmp12.i = load volatile i32* undef             ; <i32> [#uses=1]
   %conv13.i = zext i32 %tmp12.i to i64            ; <i64> [#uses=1]
   %shl.i = shl i64 %conv13.i, 32                  ; <i64> [#uses=1]
   %or.i = or i64 %shl.i, %conv.i                  ; <i64> [#uses=1]
   %add16.i = add i64 %or.i, 256                   ; <i64> [#uses=1]
   %shr.i = lshr i64 %add16.i, 8                   ; <i64> [#uses=1]
   %conv19.i = trunc i64 %shr.i to i32             ; <i32> [#uses=1]
-  volatile store i32 %conv19.i, i32* undef
+  store volatile i32 %conv19.i, i32* undef
   ret i32 undef
 }
 
@@ -203,7 +203,7 @@ entry:
 ; <rdar://problem/9187792>
 define fastcc void @func_61() nounwind sspreq {
 entry:
-  %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false)
+  %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false, i32 0)
   %t2 = icmp eq i64 %t1, -1
   br i1 %t2, label %bb2, label %bb1
 
@@ -214,7 +214,7 @@ bb2:
   ret void
 }
 
-declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone
+declare i64 @llvm.objectsize.i64(i8*, i1, i32) nounwind readnone
 
 ; PR10277
 ; This test has dead code elimination caused by remat during spilling.
@@ -316,3 +316,78 @@ declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_c
 declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
 
 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
+
+; PR10463
+; Spilling a virtual register with <undef> uses.
+define void @autogen_239_1000() {
+BB:
+    %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
+    br label %CF
+
+CF:
+    %B16 = frem <8 x double> zeroinitializer, %Shuff
+    %E19 = extractelement <8 x double> %Shuff, i32 5
+    br i1 undef, label %CF, label %CF75
+
+CF75:
+    br i1 undef, label %CF75, label %CF76
+
+CF76:
+    store double %E19, double* undef
+    br i1 undef, label %CF76, label %CF77
+
+CF77:
+    %B55 = fmul <8 x double> %B16, undef
+    br label %CF77
+}
+
+; PR10527
+define void @pr10527() nounwind uwtable {
+entry:
+  br label %"4"
+
+"3":
+  %0 = load <2 x i32>* null, align 8
+  %1 = xor <2 x i32> zeroinitializer, %0
+  %2 = and <2 x i32> %1, %6
+  %3 = or <2 x i32> undef, %2
+  %4 = and <2 x i32> %3, undef
+  store <2 x i32> %4, <2 x i32>* undef
+  %5 = load <2 x i32>* undef, align 1
+  br label %"4"
+
+"4":
+  %6 = phi <2 x i32> [ %5, %"3" ], [ zeroinitializer, %entry ]
+  %7 = icmp ult i32 undef, undef
+  br i1 %7, label %"3", label %"5"
+
+"5":
+  ret void
+}
+
+; PR11078
+;
+; A virtual register used by the "foo" inline asm memory operand gets
+; constrained to GR32_ABCD during coalescing.  This makes the inline asm
+; impossible to allocate without splitting the live range and reinflating the
+; register class around the inline asm.
+;
+; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0).
+
+@__force_order = external hidden global i32, align 4
+define void @pr11078(i32* %pgd) nounwind {
+entry:
+  %t0 = load i32* %pgd, align 4
+  %and2 = and i32 %t0, 1
+  %tobool = icmp eq i32 %and2, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+  %t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(i32* @__force_order) nounwind
+  br label %if.end
+
+if.end:
+  %t6 = inttoptr i32 %t0 to i64*
+  %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind
+  ret void
+}