Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / divide-by-constant.ll

diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll
index 545662fd0ffc82f4acf97ac5cd52f4a33ddf1bbd..e577ecb85aa83f582e3b4cae797f3d0814afa9e5 100644 (file)
--- a/test/CodeGen/X86/divide-by-constant.ll
+++ b/test/CodeGen/X86/divide-by-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=0 | FileCheck %s
+; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -asm-verbose=0 | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
 target triple = "i686-pc-linux-gnu"
 
@@ -40,7 +40,7 @@ entry:
        %div = sdiv i16 %x, 33          ; <i32> [#uses=1]
        ret i16 %div
 ; CHECK: test4:
-; CHECK: imull $-1985, %ecx, %ecx 
+; CHECK: imull $1986, %eax, %
 }
 
 define i32 @test5(i32 %A) nounwind {
@@ -51,3 +51,23 @@ define i32 @test5(i32 %A) nounwind {
 ; CHECK: mull  4(%esp)
 }
 
+define signext i16 @test6(i16 signext %x) nounwind {
+entry:
+  %div = sdiv i16 %x, 10
+  ret i16 %div
+; CHECK: test6:
+; CHECK: imull $26215, %eax, %eax
+; CHECK: shrl  $31, %ecx
+; CHECK: sarl  $18, %eax
+}
+
+define i32 @test7(i32 %x) nounwind {
+  %div = udiv i32 %x, 28
+  ret i32 %div
+; CHECK: test7:
+; CHECK: shrl $2
+; CHECK: movl $613566757
+; CHECK: mull
+; CHECK-NOT: shrl
+; CHECK: ret
+}