This commit enables unaligned memory accesses of vector types on AArch64 back end...

[oota-llvm.git] / test / CodeGen / X86 / dynamic-allocas-VLAs.ll

diff --git a/test/CodeGen/X86/dynamic-allocas-VLAs.ll b/test/CodeGen/X86/dynamic-allocas-VLAs.ll
index f9c36e3c77cfd3be4dc66d0f60f0d4a12adede56..9405f76cbed03f598132848570342055f2c7c8e7 100644 (file)
--- a/test/CodeGen/X86/dynamic-allocas-VLAs.ll
+++ b/test/CodeGen/X86/dynamic-allocas-VLAs.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s -check-prefix=FORCE-ALIGN
+; RUN: llc < %s -mcpu=generic -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mcpu=generic -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s -check-prefix=FORCE-ALIGN
 ; rdar://11496434
 
 ; no VLAs or dynamic alignment
@@ -85,26 +85,25 @@ entry:
 ; CHECK: _t4
 ; CHECK: pushq %rbp
 ; CHECK: movq %rsp, %rbp
-; CHECK: andq $-32, %rsp
 ; CHECK: pushq %r14
 ; CHECK: pushq %rbx
-; CHECK: subq $[[STACKADJ:[0-9]+]], %rsp
+; CHECK: andq $-32, %rsp
+; CHECK: subq ${{[0-9]+}}, %rsp
 ; CHECK: movq %rsp, %rbx
 ;
 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdi
 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdx
 ; CHECK: callq   _t4_helper
 ;
-; CHECK: addq $[[STACKADJ]], %rsp
+; CHECK: leaq -16(%rbp), %rsp
 ; CHECK: popq %rbx
 ; CHECK: popq %r14
-; CHECK: movq %rbp, %rsp
 ; CHECK: popq %rbp
 }
 
 declare void @t4_helper(i32*, i32*, <8 x float>*)
 
-; Dynamic realignment + Spill
+; Spilling an AVX register shouldn't cause dynamic realignment
 define i32 @t5(float* nocapture %f) nounwind uwtable ssp {
 entry:
   %a = alloca i32, align 4
@@ -117,21 +116,15 @@ entry:
   ret i32 %add
 
 ; CHECK: _t5
-; CHECK: pushq %rbp
-; CHECK: movq %rsp, %rbp
-; CHECK: andq $-32, %rsp
 ; CHECK: subq ${{[0-9]+}}, %rsp
 ;
 ; CHECK: vmovaps (%rdi), [[AVXREG:%ymm[0-9]+]]
-; CHECK: vmovaps [[AVXREG]], (%rsp)
+; CHECK: vmovups [[AVXREG]], (%rsp)
 ; CHECK: leaq {{[0-9]+}}(%rsp), %rdi
 ; CHECK: callq   _t5_helper1
-; CHECK: vmovaps (%rsp), %ymm0
+; CHECK: vmovups (%rsp), %ymm0
 ; CHECK: callq   _t5_helper2
 ; CHECK: movl {{[0-9]+}}(%rsp), %eax
-;
-; CHECK: movq %rbp, %rsp
-; CHECK: popq %rbp
 }
 
 declare void @t5_helper1(i32*)
@@ -176,19 +169,17 @@ entry:
 ; CHECK: _t7
 ; CHECK:     pushq %rbp
 ; CHECK:     movq %rsp, %rbp
-; CHECK:     andq $-32, %rsp
 ; CHECK:     pushq %rbx
-; CHECK:     subq $[[ADJ:[0-9]+]], %rsp
+; CHECK:     andq $-32, %rsp
+; CHECK:     subq ${{[0-9]+}}, %rsp
 ; CHECK:     movq %rsp, %rbx
 
 ; Stack adjustment for byval
 ; CHECK:     subq {{.*}}, %rsp
 ; CHECK:     callq _bar
 ; CHECK-NOT: addq {{.*}}, %rsp
-; CHECK:     movq %rbx, %rsp
-; CHECK:     addq $[[ADJ]], %rsp
+; CHECK:     leaq -8(%rbp), %rsp
 ; CHECK:     popq %rbx
-; CHECK:     movq %rbp, %rsp
 ; CHECK:     popq %rbp
 }
 
@@ -229,14 +220,12 @@ entry:
 ; FORCE-ALIGN: _t9
 ; FORCE-ALIGN: pushq %rbp
 ; FORCE-ALIGN: movq %rsp, %rbp
-; FORCE-ALIGN: andq $-32, %rsp
 ; FORCE-ALIGN: pushq %rbx
-; FORCE-ALIGN: subq $24, %rsp
+; FORCE-ALIGN: andq $-32, %rsp
+; FORCE-ALIGN: subq $32, %rsp
 ; FORCE-ALIGN: movq %rsp, %rbx
 
-; FORCE-ALIGN: movq %rbx, %rsp
-; FORCE-ALIGN: addq $24, %rsp
+; FORCE-ALIGN: leaq -8(%rbp), %rsp
 ; FORCE-ALIGN: popq %rbx
-; FORCE-ALIGN: movq %rbp, %rsp
 ; FORCE-ALIGN: popq %rbp
-}
\ No newline at end of file
+}