Add a neat little two's complement hack for x86.

[oota-llvm.git] / test / CodeGen / X86 / fast-cc-pass-in-regs.ll

diff --git a/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
index 6899683c4c474a64e88e3c87388d2b35ca912a4c..a96e5043fed4eecc79a21dcd2f5f7240eccccd7f 100644 (file)
--- a/test/CodeGen/X86/fast-cc-pass-in-regs.ll
+++ b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -1,16 +1,29 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'mov EDX, 1'
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | FileCheck %s
 ; check that fastcc is passing stuff in regs.
 
-; Argument reg passing is disabled due to regalloc issues.  FIXME!
-; XFAIL: *
+declare x86_fastcallcc i64 @callee(i64)
 
-declare fastcc long %callee(long)
+define i64 @caller() {
+        %X = call x86_fastcallcc  i64 @callee( i64 4294967299 )          ; <i64> [#uses=1]
+; CHECK: mov{{.*}}EDX, 1
+        ret i64 %X
+}
 
-long %caller() {
-       %X = call fastcc long %callee(long 4294967299)  ;; (1ULL << 32) + 3
-       ret long %X
+define x86_fastcallcc i64 @caller2(i64 %X) {
+        ret i64 %X
+; CHECK: mov{{.*}}EAX, ECX
 }
 
-fastcc long %caller2(long %X) {
-       ret long %X
+declare x86_thiscallcc i64 @callee2(i32)
+
+define i64 @caller3() {
+        %X = call x86_thiscallcc i64 @callee2( i32 3 )
+; CHECK: mov{{.*}}ECX, 3
+        ret i64 %X
 }
+
+define x86_thiscallcc i32 @caller4(i32 %X) {
+        ret i32 %X
+; CHECK: mov{{.*}}EAX, ECX
+}
+