Implement a feature (-vector-unaligned-mem) to allow targets to

[oota-llvm.git] / test / CodeGen / X86 / fast-isel-gep.ll

diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
index fb24f19968277c9e5234491b55dc1eb8b4ec0cf2..5b8acecc3c18c8b8aae4a9177650d62a83e9c177 100644 (file)
--- a/test/CodeGen/X86/fast-isel-gep.ll
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -1,10 +1,9 @@
 ; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -march=x86 -O0 | FileCheck %s --check-prefix=X32
-; PR3181
 
 ; GEP indices are interpreted as signed integers, so they
 ; should be sign-extended to 64 bits on 64-bit targets.
-
+; PR3181
 define i32 @test1(i32 %t3, i32* %t1) nounwind {
        %t9 = getelementptr i32* %t1, i32 %t3           ; <i32*> [#uses=1]
        %t15 = load i32* %t9            ; <i32> [#uses=1]
@@ -31,3 +30,24 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind {
 ; X64:         movl    (%rsi,%rdi,4), %eax
 ; X64:         ret
 }
+
+
+
+; PR4984
+define i8 @test3(i8* %start) nounwind {
+entry:
+  %A = getelementptr i8* %start, i64 -2               ; <i8*> [#uses=1]
+  %B = load i8* %A, align 1                       ; <i8> [#uses=1]
+  ret i8 %B
+  
+  
+; X32: test3:
+; X32:         movl    4(%esp), %eax
+; X32:         movb    -2(%eax), %al
+; X32:         ret
+
+; X64: test3:
+; X64:         movb    -2(%rdi), %al
+; X64:         ret
+
+}