Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / fast-isel-gep.ll

diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
index 1a2e34ec7f5c4b137752058c31dcf85f08d5dbfd..f0375f86028c1f050a6948d03a97dcf15331845d 100644 (file)
--- a/test/CodeGen/X86/fast-isel-gep.ll
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -82,9 +82,8 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
   ret i64 %v11
 ; X64: test5:
 ; X64: movslq  %e[[A1]], %rax
-; X64-NEXT: movq       (%r[[A0]],%rax), %rax
-; X64-NEXT: addq       %{{rdx|r8}}, %rax
-; X64-NEXT: ret
+; X64-NEXT: (%r[[A0]],%rax),
+; X64: ret
 }
 
 ; PR9500, rdar://9156159 - Don't do non-local address mode folding,
@@ -104,6 +103,36 @@ invoke.cont16:                                    ; preds = %if.then14
   unreachable
 
 lpad:                                             ; preds = %if.end19, %if.then14, %if.end, %entry
+  %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+            cleanup
   unreachable
 }
 declare i8* @_ZNK18G__FastAllocString4dataEv() nounwind
+
+
+; PR10605 / rdar://9930964 - Don't fold loads incorrectly.  The load should
+; happen before the store.  
+define i32 @test7({i32,i32,i32}* %tmp1, i32 %tmp71, i32 %tmp63) nounwind  {
+; X64: test7:
+; X64:    movl 8({{%rdi|%rcx}}), %eax
+; X64:     movl        $4, 8({{%rdi|%rcx}})
+
+
+  %tmp29 = getelementptr inbounds {i32,i32,i32}* %tmp1, i32 0, i32 2
+  %tmp30 = load i32* %tmp29, align 4
+
+  %p2 = getelementptr inbounds {i32,i32,i32}* %tmp1, i32 0, i32 2
+  store i32 4, i32* %p2
+  
+  %tmp72 = or i32 %tmp71, %tmp30
+  %tmp73 = icmp ne i32 %tmp63, 32
+  br i1 %tmp73, label %T, label %F
+
+T:
+  ret i32 %tmp72
+
+F:
+  ret i32 4
+}
+
+declare i32 @__gxx_personality_v0(...)