Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / inline-asm.ll

diff --git a/test/CodeGen/X86/inline-asm.ll b/test/CodeGen/X86/inline-asm.ll
index de145091886be17a1cdc4b6fe56f9fdabfde4218..eef6c2f377a7b61a073d79187da92e75c7a032be 100644 (file)
--- a/test/CodeGen/X86/inline-asm.ll
+++ b/test/CodeGen/X86/inline-asm.ll
@@ -1,8 +1,45 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
 
-int %test1() {
+define i32 @test1() nounwind {
        ; Dest is AX, dest type = i32.
-        %tmp4 = call int asm sideeffect "FROB %0", "={ax}"()
-        ret int %tmp4
+        %tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"()
+        ret i32 %tmp4
 }
 
+define void @test2(i32 %V) nounwind {
+       ; input is AX, in type = i32.
+        call void asm sideeffect "FROB $0", "{ax}"(i32 %V)
+        ret void
+}
+
+define void @test3() nounwind {
+        ; FP constant as a memory operand.
+        tail call void asm sideeffect "frob $0", "m"( float 0x41E0000000000000)
+        ret void
+}
+
+define void @test4() nounwind {
+       ; J means a constant in range 0 to 63.
+       tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind
+       ret void
+}
+
+; rdar://9738585
+define i32 @test5() nounwind {
+entry:
+  %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind
+  ret i32 0
+}
+
+; rdar://9777108 PR10352
+define void @test6(i1 zeroext %desired) nounwind {
+entry:
+  tail call void asm sideeffect "foo $0", "q,~{dirflag},~{fpsr},~{flags}"(i1 %desired) nounwind
+  ret void
+}
+
+define void @test7(i1 zeroext %desired, i32* %p) nounwind {
+entry:
+  %0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind
+  ret void
+}