Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / jump_sign.ll

diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll
index aed39bf8a1ececfc387a16e96645441ec25be634..94cbe5d1937c4437369471336cb30a30b567965b 100644 (file)
--- a/test/CodeGen/X86/jump_sign.ll
+++ b/test/CodeGen/X86/jump_sign.ll
@@ -1,20 +1,85 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep jns
-int %f(int %X) {
+; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
+
+define i32 @f(i32 %X) {
 entry:
-        %tmp1 = add int %X, 1           ; <int> [#uses=1]
-        %tmp = setlt int %tmp1, 0               ; <bool> [#uses=1]
-        br bool %tmp, label %cond_true, label %cond_next
+; CHECK: f:
+; CHECK: jns
+       %tmp1 = add i32 %X, 1           ; <i32> [#uses=1]
+       %tmp = icmp slt i32 %tmp1, 0            ; <i1> [#uses=1]
+       br i1 %tmp, label %cond_true, label %cond_next
 
-cond_true:              ; preds = %entry
-        %tmp2 = tail call int (...)* %bar( )            ; <int> [#uses=0]
-        br label %cond_next
+cond_true:             ; preds = %entry
+       %tmp2 = tail call i32 (...)* @bar( )            ; <i32> [#uses=0]
+       br label %cond_next
 
-cond_next:              ; preds = %entry, %cond_true
-        %tmp3 = tail call int (...)* %baz( )            ; <int> [#uses=0]
-        ret int undef
+cond_next:             ; preds = %cond_true, %entry
+       %tmp3 = tail call i32 (...)* @baz( )            ; <i32> [#uses=0]
+       ret i32 undef
 }
 
-declare int %bar(...)
+declare i32 @bar(...)
+
+declare i32 @baz(...)
 
-declare int %baz(...)
+; rdar://10633221
+; rdar://11355268
+define i32 @g(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: g:
+; CHECK-NOT: test
+; CHECK: cmovs
+  %sub = sub nsw i32 %a, %b
+  %cmp = icmp sgt i32 %sub, 0
+  %cond = select i1 %cmp, i32 %sub, i32 0
+  ret i32 %cond
+}
 
+; rdar://10734411
+define i32 @h(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: h:
+; CHECK-NOT: cmp
+; CHECK: cmov
+; CHECK-NOT: movl
+; CHECK: ret
+  %cmp = icmp slt i32 %b, %a
+  %sub = sub nsw i32 %a, %b
+  %cond = select i1 %cmp, i32 %sub, i32 0
+  ret i32 %cond
+}
+define i32 @i(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: i:
+; CHECK-NOT: cmp
+; CHECK: cmov
+; CHECK-NOT: movl
+; CHECK: ret
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sub nsw i32 %a, %b
+  %cond = select i1 %cmp, i32 %sub, i32 0
+  ret i32 %cond
+}
+define i32 @j(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: j:
+; CHECK-NOT: cmp
+; CHECK: cmov
+; CHECK-NOT: movl
+; CHECK: ret
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sub i32 %a, %b
+  %cond = select i1 %cmp, i32 %sub, i32 0
+  ret i32 %cond
+}
+define i32 @k(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: k:
+; CHECK-NOT: cmp
+; CHECK: cmov
+; CHECK-NOT: movl
+; CHECK: ret
+  %cmp = icmp ult i32 %b, %a
+  %sub = sub i32 %a, %b
+  %cond = select i1 %cmp, i32 %sub, i32 0
+  ret i32 %cond
+}