[x32] Fix FrameIndex check in SelectLEA64_32Addr

[oota-llvm.git] / test / CodeGen / X86 / lsr-reuse-trunc.ll

diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll
index a663a220e62d3fc0a930e16b3b3c90d06e908cba..276dab72f7cc6cebd46443247b774b1bf3047f75 100644 (file)
--- a/test/CodeGen/X86/lsr-reuse-trunc.ll
+++ b/test/CodeGen/X86/lsr-reuse-trunc.ll
@@ -1,21 +1,15 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux -mcpu=nehalem | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=nehalem | FileCheck %s
 
 ; Full strength reduction wouldn't reduce register pressure, so LSR should
 ; stick with indexing here.
 
-; Also checks andps and andnps shares the same constantpool. Previously llvm
-; will codegen two andps, one using 0x80000000, the other 0x7fffffff.
-; rdar://7323335
-
-; CHECK: movaps LCPI1_0
-; CHECK: movaps LCPI1_1
-; CHECK-NOT: movaps LCPI1_2
-; CHECK: movaps (%rsi,%rax,4), %xmm2
-; CHECK: andps
-; CHECK: andnps
-; CHECK: movaps %xmm2, (%rdi,%rax,4)
+; CHECK: movaps        (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
+; CHECK: cvtdq2ps
+; CHECK: orps          {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
+; CHECK: movaps        [[X4]], (%{{rdi|rcx}},%rax,4)
 ; CHECK: addq  $4, %rax
-; CHECK: cmpl  %eax, (%rdx)
+; CHECK: cmpl  %eax, (%{{rdx|r8}})
 ; CHECK-NEXT: jg
 
 define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {