CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / lzcnt.ll

diff --git a/test/CodeGen/X86/lzcnt.ll b/test/CodeGen/X86/lzcnt.ll
index c2b3e68cbd21d3a3dd7db001babcda7d5ac366ee..ff83f8540946e735f7e6de59e97a89cfac4b7f6e 100644 (file)
--- a/test/CodeGen/X86/lzcnt.ll
+++ b/test/CodeGen/X86/lzcnt.ll
@@ -8,27 +8,55 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 define i8 @t1(i8 %x) nounwind  {
        %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
        ret i8 %tmp
-; CHECK: t1:
-; CHECK: lzcntw
+; CHECK-LABEL: t1:
+; CHECK: lzcntl
 }
 
 define i16 @t2(i16 %x) nounwind  {
        %tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
        ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: lzcntw
 }
 
 define i32 @t3(i32 %x) nounwind  {
        %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
        ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: lzcntl
 }
 
 define i64 @t4(i64 %x) nounwind  {
        %tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
        ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
+; CHECK: lzcntq
+}
+
+define i8 @t5(i8 %x) nounwind  {
+       %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
+       ret i8 %tmp
+; CHECK-LABEL: t5:
+; CHECK: lzcntl
+}
+
+define i16 @t6(i16 %x) nounwind  {
+       %tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
+       ret i16 %tmp
+; CHECK-LABEL: t6:
+; CHECK: lzcntw
+}
+
+define i32 @t7(i32 %x) nounwind  {
+       %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
+       ret i32 %tmp
+; CHECK-LABEL: t7:
+; CHECK: lzcntl
+}
+
+define i64 @t8(i64 %x) nounwind  {
+       %tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
+       ret i64 %tmp
+; CHECK-LABEL: t8:
 ; CHECK: lzcntq
 }