CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / misaligned-memset.ll

diff --git a/test/CodeGen/X86/misaligned-memset.ll b/test/CodeGen/X86/misaligned-memset.ll
index 21f8bf2bf29eebc3a45091beb735c04ff8f60689..ef8e0e81ad77bfaa1991cbc3c234d2a7e3b908bb 100644 (file)
--- a/test/CodeGen/X86/misaligned-memset.ll
+++ b/test/CodeGen/X86/misaligned-memset.ll
@@ -7,8 +7,8 @@ define i32 @main() nounwind ssp {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  call void @llvm.memset.p0i8.i64(i8* bitcast (i64* getelementptr inbounds ([3 x i64]* @a, i32 0, i64 1) to i8*), i8 0, i64 16, i32 1, i1 false)
-  %0 = load i32* %retval
+  call void @llvm.memset.p0i8.i64(i8* bitcast (i64* getelementptr inbounds ([3 x i64], [3 x i64]* @a, i32 0, i64 1) to i8*), i8 0, i64 16, i32 1, i1 false)
+  %0 = load i32, i32* %retval
   ret i32 %0
 }