CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / mmx-arg-passing.ll

diff --git a/test/CodeGen/X86/mmx-arg-passing.ll b/test/CodeGen/X86/mmx-arg-passing.ll
index b348512b579858b7105d2104ff15bae6a21c12c9..67ccb9e32dde0e7a580c58f3a403283db99de224 100644 (file)
--- a/test/CodeGen/X86/mmx-arg-passing.ll
+++ b/test/CodeGen/X86/mmx-arg-passing.ll
@@ -1,8 +1,6 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 1
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | not grep movups
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | FileCheck %s --check-prefix=X86-32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86-64
 ;
 ; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
 ; On Darwin x86-32, v1i64 values are passed in memory.  In this example, they
@@ -13,6 +11,18 @@
 @u1 = external global x86_mmx
 
 define void @t1(x86_mmx %v1) nounwind  {
+; X86-32-LABEL: t1:
+; X86-32:       ## BB#0:
+; X86-32-NEXT:    movl L_u1$non_lazy_ptr, %eax
+; X86-32-NEXT:    movq %mm0, (%eax)
+; X86-32-NEXT:    retl
+;
+; X86-64-LABEL: t1:
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    movdq2q %xmm0, %mm0
+; X86-64-NEXT:    movq _u1@{{.*}}(%rip), %rax
+; X86-64-NEXT:    movq %mm0, (%rax)
+; X86-64-NEXT:    retq
        store x86_mmx %v1, x86_mmx* @u1, align 8
        ret void
 }
@@ -20,8 +30,21 @@ define void @t1(x86_mmx %v1) nounwind  {
 @u2 = external global x86_mmx
 
 define void @t2(<1 x i64> %v1) nounwind  {
+; X86-32-LABEL: t2:
+; X86-32:       ## BB#0:
+; X86-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-32-NEXT:    movl L_u2$non_lazy_ptr, %edx
+; X86-32-NEXT:    movl %ecx, 4(%edx)
+; X86-32-NEXT:    movl %eax, (%edx)
+; X86-32-NEXT:    retl
+;
+; X86-64-LABEL: t2:
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    movq _u2@{{.*}}(%rip), %rax
+; X86-64-NEXT:    movq %rdi, (%rax)
+; X86-64-NEXT:    retq
         %tmp = bitcast <1 x i64> %v1 to x86_mmx
        store x86_mmx %tmp, x86_mmx* @u2, align 8
        ret void
 }
-