Implement PR3495: local spiller optimization. The local spiller can now keep availabi...

[oota-llvm.git] / test / CodeGen / X86 / mmx-shift.ll

diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll
index 82eeafd07527e3cfcf46eb180f0179bd7c58f28f..277cf075cb93025b1c6314ae1a86db7058cfe9ea 100644 (file)
--- a/test/CodeGen/X86/mmx-shift.ll
+++ b/test/CodeGen/X86/mmx-shift.ll
@@ -1,6 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psllq | grep 32
 ; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psllq | grep 32
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psrad
+; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psrlw
 
 define i64 @t1(<1 x i64> %mm1) nounwind  {
 entry:
@@ -19,3 +20,13 @@ entry:
 }
 
 declare <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32>, <2 x i32>) nounwind readnone 
+
+define i64 @t3(<1 x i64> %mm1, i32 %bits) nounwind  {
+entry:
+       %tmp6 = bitcast <1 x i64> %mm1 to <4 x i16>             ; <<4 x i16>> [#uses=1]
+       %tmp8 = tail call <4 x i16> @llvm.x86.mmx.psrli.w( <4 x i16> %tmp6, i32 %bits ) nounwind readnone               ; <<4 x i16>> [#uses=1]
+       %retval1314 = bitcast <4 x i16> %tmp8 to i64            ; <i64> [#uses=1]
+       ret i64 %retval1314
+}
+
+declare <4 x i16> @llvm.x86.mmx.psrli.w(<4 x i16>, i32) nounwind readnone