Ignore DBG_VALUE machine instructions while constructing instruction ranges based...

[oota-llvm.git] / test / CodeGen / X86 / movgs.ll

diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll
index 3a249470d46890d1d22f9ec4694d1ff636b24b65..00190e802fc94e1c74fcf38ee268c0965dcf915b 100644 (file)
--- a/test/CodeGen/X86/movgs.ll
+++ b/test/CodeGen/X86/movgs.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s --check-prefix=X64
 
 define i32 @test1() nounwind readonly {
 entry:
@@ -26,8 +26,32 @@ entry:
 
 ; rdar://8453210
 ; X32: test2:
-; X32: movl    16(%esp), %eax
-; X32: call    *%gs:(%eax)
+; X32: movl    {{.*}}(%esp), %eax
+; X32: calll   *%gs:(%eax)
 
 ; X64: test2:
 ; X64: callq   *%gs:(%rdi)
+
+
+
+
+define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly {
+entry:
+  %0 = load i64 addrspace(256)* %p
+  %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0
+  %1 = bitcast <2 x i64> %tmp2 to <8 x i16>
+  %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
+  %3 = bitcast <4 x i32> %2 to <2 x i64>
+  ret <2 x i64> %3
+  
+; X32: pmovsxwd_1:
+; X32:         movl    4(%esp), %eax
+; X32:         pmovsxwd        %gs:(%eax), %xmm0
+; X32:         ret
+
+; X64: pmovsxwd_1:
+; X64: pmovsxwd        %gs:(%rdi), %xmm0
+; X64: ret
+}
+
+declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone