Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / or-branch.ll

diff --git a/test/CodeGen/X86/or-branch.ll b/test/CodeGen/X86/or-branch.ll
index 5ad7fa14b358c18c4d8004b42990da68339595f7..9ebf8901b77c067bba16142e140b8c6f5ab8d2d2 100644 (file)
--- a/test/CodeGen/X86/or-branch.ll
+++ b/test/CodeGen/X86/or-branch.ll
@@ -1,19 +1,19 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep set
+; RUN: llc < %s -march=x86  | not grep set
 
-void %foo(int %X, int %Y, int %Z) {
+define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
 entry:
-       %tmp = tail call int (...)* %bar( )             ; <int> [#uses=0]
-       %tmp = seteq int %X, 0          ; <bool> [#uses=1]
-       %tmp3 = setlt int %Y, 5         ; <bool> [#uses=1]
-       %tmp4 = or bool %tmp3, %tmp             ; <bool> [#uses=1]
-       br bool %tmp4, label %cond_true, label %UnifiedReturnBlock
+       %tmp = tail call i32 (...)* @bar( )             ; <i32> [#uses=0]
+       %tmp.upgrd.1 = icmp eq i32 %X, 0                ; <i1> [#uses=1]
+       %tmp3 = icmp slt i32 %Y, 5              ; <i1> [#uses=1]
+       %tmp4 = or i1 %tmp3, %tmp.upgrd.1               ; <i1> [#uses=1]
+       br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:             ; preds = %entry
-       %tmp5 = tail call int (...)* %bar( )            ; <int> [#uses=0]
+       %tmp5 = tail call i32 (...)* @bar( )            ; <i32> [#uses=0]
        ret void
 
 UnifiedReturnBlock:            ; preds = %entry
        ret void
 }
 
-declare int %bar(...)
+declare i32 @bar(...)