CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / peep-test-3.ll

diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll
index a96351a30377237ea007589db83dd910ef2406d4..b3d4f585f45df50f3b3490dbadee6e4d9273b47b 100644 (file)
--- a/test/CodeGen/X86/peep-test-3.ll
+++ b/test/CodeGen/X86/peep-test-3.ll
@@ -1,15 +1,16 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -mcpu=generic -march=x86 -post-RA-scheduler=false | FileCheck %s
+; rdar://7226797
 
 ; LLVM should omit the testl and use the flags result from the orl.
 
-; CHECK: or:
+; CHECK-LABEL: or:
 define void @or(float* %A, i32 %IA, i32 %N) nounwind {
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
   %1 = and i32 %0, 3                              ; <i32> [#uses=1]
   %2 = xor i32 %IA, 1                             ; <i32> [#uses=1]
-; CHECK:      orl %ecx, %edx
-; CHECK-NEXT: je  .LBB1_2
+; CHECK:      orl %e
+; CHECK-NEXT: je
   %3 = or i32 %2, %1                              ; <i32> [#uses=1]
   %4 = icmp eq i32 %3, 0                          ; <i1> [#uses=1]
   br i1 %4, label %return, label %bb
@@ -21,13 +22,13 @@ bb:                                               ; preds = %entry
 return:                                           ; preds = %entry
   ret void
 }
-; CHECK: xor:
+; CHECK-LABEL: xor:
 define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
   %1 = and i32 %0, 3                              ; <i32> [#uses=1]
 ; CHECK:      xorl $1, %e
-; CHECK-NEXT: je   .LBB2_2
+; CHECK-NEXT: je
   %2 = xor i32 %IA, 1                             ; <i32> [#uses=1]
   %3 = xor i32 %2, %1                              ; <i32> [#uses=1]
   %4 = icmp eq i32 %3, 0                          ; <i1> [#uses=1]
@@ -40,7 +41,7 @@ bb:                                               ; preds = %entry
 return:                                           ; preds = %entry
   ret void
 }
-; CHECK: and:
+; CHECK-LABEL: and:
 define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
 entry:
   store i8 0, i8* %p
@@ -49,7 +50,7 @@ entry:
   %2 = xor i32 %IA, 1                             ; <i32> [#uses=1]
 ; CHECK:      andl  $3, %
 ; CHECK-NEXT: movb  %
-; CHECK-NEXT: je    .LBB3_2
+; CHECK-NEXT: je
   %3 = and i32 %2, %1                              ; <i32> [#uses=1]
   %t = trunc i32 %3 to i8
   store i8 %t, i8* %p
@@ -64,9 +65,9 @@ return:                                           ; preds = %entry
   ret void
 }
 
-; Just like @and, but without the trunc+store. This should use a testl
+; Just like @and, but without the trunc+store. This should use a testb
 ; instead of an andl.
-; CHECK: test:
+; CHECK-LABEL: test:
 define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
 entry:
   store i8 0, i8* %p
@@ -74,7 +75,7 @@ entry:
   %1 = and i32 %0, 3                              ; <i32> [#uses=1]
   %2 = xor i32 %IA, 1                             ; <i32> [#uses=1]
 ; CHECK:      testb $3, %
-; CHECK-NEXT: je    .LBB4_2
+; CHECK-NEXT: je
   %3 = and i32 %2, %1                              ; <i32> [#uses=1]
   %4 = icmp eq i32 %3, 0                          ; <i1> [#uses=1]
   br i1 %4, label %return, label %bb