CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / phys_subreg_coalesce-3.ll

diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
index 6eb97c3cd7ab7e2c912d35a946fa477b9aae80ad..74e3d1291c05aa21e691c684aad38ef8c4a84418 100644 (file)
--- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
 ; rdar://5571034
 
 ; This requires physreg joining, %vreg13 is live everywhere:
@@ -25,11 +25,11 @@ bb:                                               ; preds = %bb, %bb.nph
   %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
   %j.06 = sub i32 %j.03, %indvar                  ; <i32> [#uses=1]
   %tmp11 = sub i32 %tmp10, %indvar                ; <i32> [#uses=1]
-  %scevgep = getelementptr i32* %ptr, i32 %tmp11  ; <i32*> [#uses=1]
-  %1 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %scevgep = getelementptr i32, i32* %ptr, i32 %tmp11  ; <i32*> [#uses=1]
+  %1 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %2 = ashr i32 %j.06, %shifts                    ; <i32> [#uses=1]
   %3 = and i32 %2, 65535                          ; <i32> [#uses=1]
-  %4 = getelementptr inbounds i32* %quadrant, i32 %1 ; <i32*> [#uses=1]
+  %4 = getelementptr inbounds i32, i32* %quadrant, i32 %1 ; <i32*> [#uses=1]
   store i32 %3, i32* %4, align 4
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
   %exitcond = icmp eq i32 %indvar.next, %bbSize   ; <i1> [#uses=1]