Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / X86 / pr12360.ll

diff --git a/test/CodeGen/X86/pr12360.ll b/test/CodeGen/X86/pr12360.ll
index c0af432cc8b5635cb30ad1ed8eb09e603f9dc180..f29e50e29a3b7f4552892a09abb20c8643c1ed0a 100644 (file)
--- a/test/CodeGen/X86/pr12360.ll
+++ b/test/CodeGen/X86/pr12360.ll
@@ -1,14 +1,46 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 define zeroext i1 @f1(i8* %x) {
+; CHECK: f1:
+; CHECK: movb  (%rdi), %al
+; CHECK-NEXT: ret
+
 entry:
   %0 = load i8* %x, align 1, !range !0
   %tobool = trunc i8 %0 to i1
   ret i1 %tobool
 }
 
-; CHECK: f1:
+define zeroext i1 @f2(i8* %x) {
+; CHECK: f2:
 ; CHECK: movb  (%rdi), %al
 ; CHECK-NEXT: ret
 
+entry:
+  %0 = load i8* %x, align 1, !range !0
+  %tobool = icmp ne i8 %0, 0
+  ret i1 %tobool
+}
+
 !0 = metadata !{i8 0, i8 2}
+
+
+; check that we don't build a "trunc" from i1 to i1, which would assert.
+define zeroext i1 @f3(i1 %x) {
+; CHECK: f3:
+
+entry:
+  %tobool = icmp ne i1 %x, 0
+  ret i1 %tobool
+}
+
+; check that we don't build a trunc when other bits are needed
+define zeroext i1 @f4(i32 %x) {
+; CHECK: f4:
+; CHECK: and
+
+entry:
+  %y = and i32 %x, 32768
+  %z = icmp ne i32 %y, 0
+  ret i1 %z
+}