Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / prefetch.ll

diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll
index fac5915aae8873fb1caecb07f0b790e4e052a6da..ec2f302b14993da27c3e9ff32d7bfd11d89d64a3 100644 (file)
--- a/test/CodeGen/X86/prefetch.ll
+++ b/test/CodeGen/X86/prefetch.ll
@@ -1,16 +1,19 @@
-; RUN: llc < %s -march=x86 -mattr=+sse > %t
-; RUN: grep prefetchnta %t
-; RUN: grep prefetcht0 %t
-; RUN: grep prefetcht1 %t
-; RUN: grep prefetcht2 %t
+; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
+
+; rdar://10538297
 
 define void @t(i8* %ptr) nounwind  {
 entry:
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
+; CHECK: prefetcht2
+; CHECK: prefetcht1
+; CHECK: prefetcht0
+; CHECK: prefetchnta
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
        ret void
 }
 
-declare void @llvm.prefetch(i8*, i32, i32) nounwind 
+declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind