Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / X86 / prefetch.ll

diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll
index 48d2673e4884f33d009d58c4ff35acd7d7042d09..ec2f302b14993da27c3e9ff32d7bfd11d89d64a3 100644 (file)
--- a/test/CodeGen/X86/prefetch.ll
+++ b/test/CodeGen/X86/prefetch.ll
@@ -1,4 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
+
+; rdar://10538297
 
 define void @t(i8* %ptr) nounwind  {
 entry:
@@ -6,11 +9,11 @@ entry:
 ; CHECK: prefetcht1
 ; CHECK: prefetcht0
 ; CHECK: prefetchnta
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
        ret void
 }
 
-declare void @llvm.prefetch(i8*, i32, i32) nounwind 
+declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind