This commit enables unaligned memory accesses of vector types on AArch64 back end...

[oota-llvm.git] / test / CodeGen / X86 / rdseed.ll

diff --git a/test/CodeGen/X86/rdseed.ll b/test/CodeGen/X86/rdseed.ll
index edc5069e5b0fbef29573b8262445a34d08f93d4a..c219b4ad27ece8f6f855315bd47bdad6d5e41e13 100644 (file)
--- a/test/CodeGen/X86/rdseed.ll
+++ b/test/CodeGen/X86/rdseed.ll
@@ -12,10 +12,10 @@ define i32 @_rdseed16_step(i16* %random_val) {
   ret i32 %isvalid
 ; CHECK-LABEL: _rdseed16_step:
 ; CHECK: rdseedw       %ax
-; CHECK: movw  %ax, (%r[[A0:di|cx]])
 ; CHECK: movzwl        %ax, %ecx
 ; CHECK: movl  $1, %eax
 ; CHECK: cmovael       %ecx, %eax
+; CHECK: movw  %cx, (%r[[A0:di|cx]])
 ; CHECK: ret
 }
 
@@ -27,9 +27,9 @@ define i32 @_rdseed32_step(i32* %random_val) {
   ret i32 %isvalid
 ; CHECK-LABEL: _rdseed32_step:
 ; CHECK: rdseedl       %e[[T0:[a-z]+]]
-; CHECK: movl  %e[[T0]], (%r[[A0]])
 ; CHECK: movl  $1, %eax
 ; CHECK: cmovael       %e[[T0]], %eax
+; CHECK: movl  %e[[T0]], (%r[[A0]])
 ; CHECK: ret
 }
 
@@ -41,8 +41,8 @@ define i32 @_rdseed64_step(i64* %random_val) {
   ret i32 %isvalid
 ; CHECK-LABEL: _rdseed64_step:
 ; CHECK: rdseedq       %r[[T1:[a-z]+]]
-; CHECK: movq  %r[[T1]], (%r[[A0]])
 ; CHECK: movl  $1, %eax
 ; CHECK: cmovael       %e[[T1]], %eax
+; CHECK: movq  %r[[T1]], (%r[[A0]])
 ; CHECK: ret
 }