CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / ret-mmx.ll

diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll
index fe9380585de38bf1e113d3404dda4f9fa78a9842..fc9c78d1bbeba4cff2c37d6d9c331a4c997cfffc 100644 (file)
--- a/test/CodeGen/X86/ret-mmx.ll
+++ b/test/CodeGen/X86/ret-mmx.ll
@@ -1,13 +1,40 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mcpu=core2 -mattr=+mmx,+sse2 | FileCheck %s
 ; rdar://6602459
 
 @g_v1di = external global <1 x i64>
 
-define void @test_v1di() nounwind {
+define void @t1() nounwind {
 entry:
        %call = call <1 x i64> @return_v1di()           ; <<1 x i64>> [#uses=0]
        store <1 x i64> %call, <1 x i64>* @g_v1di
         ret void
+; CHECK-LABEL: t1:
+; CHECK: callq
+; CHECK-NEXT: movq     _g_v1di
+; CHECK-NEXT: movq     %rax,
 }
 
 declare <1 x i64> @return_v1di()
+
+define <1 x i64> @t2() nounwind {
+       ret <1 x i64> <i64 1>
+; CHECK-LABEL: t2:
+; CHECK: movl  $1
+; CHECK-NEXT: ret
+}
+
+define <2 x i32> @t3() nounwind {
+       ret <2 x i32> <i32 1, i32 0>
+; CHECK-LABEL: t3:
+; CHECK: movl $1
+; CHECK: movd {{.*}}, %xmm0
+}
+
+define double @t4() nounwind {
+       ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
+; CHECK-LABEL: t4:
+; CHECK: movl $1
+; CHECK-NOT: pshufd
+; CHECK: movd {{.*}}, %xmm0
+}
+