CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / scalar_sse_minmax.ll

diff --git a/test/CodeGen/X86/scalar_sse_minmax.ll b/test/CodeGen/X86/scalar_sse_minmax.ll
index b2217f9975bd2bdfe1ec33b28d7437f156ed11bb..5ca3f85ce029897fca03005b1e9108ccff7cc382 100644 (file)
--- a/test/CodeGen/X86/scalar_sse_minmax.ll
+++ b/test/CodeGen/X86/scalar_sse_minmax.ll
@@ -1,37 +1,53 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1,+sse2 | grep mins | wc -l | grep 2 &&
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1,+sse2 | grep maxs | wc -l | grep 2
-
-declare bool %llvm.isunordered.f64( double %x, double %y )
-declare bool %llvm.isunordered.f32( float %x, float %y )
-
-implementation
-
-float %min1(float %x, float %y) {
-        %tmp = setlt float %x, %y               ; <bool> [#uses=1]
-        %retval = select bool %tmp, float %x, float %y          ; <float> [#uses=1]
-        ret float %retval
-}
-double %min2(double %x, double %y) {
-        %tmp = setlt double %x, %y
-        %retval = select bool %tmp, double %x, double %y
-        ret double %retval
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | FileCheck %s
+
+define float @min1(float %x, float %y) {
+; CHECK-LABEL: min1
+; CHECK: mins
+       %tmp = fcmp olt float %x, %y
+       %retval = select i1 %tmp, float %x, float %y
+       ret float %retval
 }
 
-float %max1(float %x, float %y) {
-        %tmp = setge float %x, %y               ; <bool> [#uses=1]
-        %tmp2 = tail call bool %llvm.isunordered.f32( float %x, float %y )
-        %tmp3 = or bool %tmp2, %tmp             ; <bool> [#uses=1]
-        %retval = select bool %tmp3, float %x, float %y         
-        ret float %retval
+define double @min2(double %x, double %y) {
+; CHECK-LABEL: min2
+; CHECK: mins
+       %tmp = fcmp olt double %x, %y
+       %retval = select i1 %tmp, double %x, double %y
+       ret double %retval
 }
 
-double %max2(double %x, double %y) {
-        %tmp = setge double %x, %y               ; <bool> [#uses=1]
-        %tmp2 = tail call bool %llvm.isunordered.f64( double %x, double %y )
-        %tmp3 = or bool %tmp2, %tmp             ; <bool> [#uses=1]
-        %retval = select bool %tmp3, double %x, double %y
-        ret double %retval
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
+define <4 x float> @min3(float %x, float %y) {
+; CHECK-LABEL: min3
+; CHECK: mins
+       %vec0 = insertelement <4 x float> undef, float %x, i32 0
+       %vec1 = insertelement <4 x float> undef, float %y, i32 0
+       %retval = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %vec0, <4 x float> %vec1)
+       ret <4 x float> %retval
 }
 
+define float @max1(float %x, float %y) {
+; CHECK-LABEL: max1
+; CHECK: maxs
+       %tmp = fcmp uge float %x, %y
+       %retval = select i1 %tmp, float %x, float %y
+       ret float %retval
+}
 
+define double @max2(double %x, double %y) {
+; CHECK-LABEL: max2
+; CHECK: maxs
+       %tmp = fcmp uge double %x, %y
+       %retval = select i1 %tmp, double %x, double %y
+       ret double %retval
+}
 
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
+define <4 x float> @max3(float %x, float %y) {
+; CHECK-LABEL: max3
+; CHECK: maxs
+       %vec0 = insertelement <4 x float> undef, float %x, i32 0
+       %vec1 = insertelement <4 x float> undef, float %y, i32 0
+       %retval = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %vec0, <4 x float> %vec1)
+       ret <4 x float> %retval
+}