; Verify that the fmul gets sunk into the one part of the diamond where it is
; needed.
; CHECK: test6:
-; CHECK: jne
-; CHECK: mulps
+; CHECK: je
; CHECK: ret
+; CHECK: mulps
; CHECK: ret
}
%val = sub <6 x i32> %x, < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
store <6 x i32> %val, <6 x i32>* %dst.addr
ret void
-
+
; CHECK: test8:
}
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
+define i32 @test13(i32 %a, i32 %b) nounwind {
+ %c = icmp ult i32 %a, %b
+ %d = sext i1 %c to i32
+ ret i32 %d
+; CHECK: test13:
+; CHECK: cmpl
+; CHECK-NEXT: sbbl
+; CHECK-NEXT: ret
+}
+define i32 @test14(i32 %a, i32 %b) nounwind {
+ %c = icmp uge i32 %a, %b
+ %d = sext i1 %c to i32
+ ret i32 %d
+; CHECK: test14:
+; CHECK: cmpl
+; CHECK-NEXT: sbbl
+; CHECK-NEXT: notl
+; CHECK-NEXT: ret
+}
+; rdar://10961709
+define i32 @test15(i32 %x) nounwind {
+entry:
+ %cmp = icmp ne i32 %x, 0
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+; CHECK: test15:
+; CHECK: negl
+; CHECK: sbbl
+}
+define i64 @test16(i64 %x) nounwind uwtable readnone ssp {
+entry:
+ %cmp = icmp ne i64 %x, 0
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+; CHECK: test16:
+; CHECK: negq
+; CHECK: sbbq
+}
+define i16 @test17(i16 %x) nounwind {
+entry:
+ %cmp = icmp ne i16 %x, 0
+ %sub = sext i1 %cmp to i16
+ ret i16 %sub
+; CHECK: test17:
+; CHECK: negw
+; CHECK: sbbw
+}