CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / shift-coalesce.ll

diff --git a/test/CodeGen/X86/shift-coalesce.ll b/test/CodeGen/X86/shift-coalesce.ll
index d38f9a88fcd6c893d86fc6f37d3b6dc49067816b..dee7d373dceea2d35489bbfe88f40ab5c6e9d2d2 100644 (file)
--- a/test/CodeGen/X86/shift-coalesce.ll
+++ b/test/CodeGen/X86/shift-coalesce.ll
@@ -1,12 +1,12 @@
 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   grep {shld.*CL}
+; RUN:   grep "shld.*cl"
 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   not grep {mov CL, BL}
+; RUN:   not grep "mov cl, bl"
 
 ; PR687
 
 define i64 @foo(i64 %x, i64* %X) {
-        %tmp.1 = load i64* %X           ; <i64> [#uses=1]
+        %tmp.1 = load i64, i64* %X           ; <i64> [#uses=1]
         %tmp.3 = trunc i64 %tmp.1 to i8         ; <i8> [#uses=1]
         %shift.upgrd.1 = zext i8 %tmp.3 to i64          ; <i64> [#uses=1]
         %tmp.4 = shl i64 %x, %shift.upgrd.1             ; <i64> [#uses=1]