CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / shift-folding.ll

diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll
index ea9002c397b8bb91245070385a150a25f13c26fd..69887870897785ffcb9cac66b0c55ea40a656116 100644 (file)
--- a/test/CodeGen/X86/shift-folding.ll
+++ b/test/CodeGen/X86/shift-folding.ll
@@ -9,7 +9,7 @@ define i32* @test1(i32* %P, i32 %X) {
 entry:
   %Y = lshr i32 %X, 2
   %gep.upgrd.1 = zext i32 %Y to i64
-  %P2 = getelementptr i32* %P, i64 %gep.upgrd.1
+  %P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.1
   ret i32* %P2
 }
 
@@ -22,7 +22,7 @@ define i32* @test2(i32* %P, i32 %X) {
 entry:
   %Y = shl i32 %X, 2
   %gep.upgrd.2 = zext i32 %Y to i64
-  %P2 = getelementptr i32* %P, i64 %gep.upgrd.2
+  %P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.2
   ret i32* %P2
 }
 
@@ -34,7 +34,7 @@ define i32* @test3(i32* %P, i32 %X) {
 
 entry:
   %Y = ashr i32 %X, 2
-  %P2 = getelementptr i32* %P, i32 %Y
+  %P2 = getelementptr i32, i32* %P, i32 %Y
   ret i32* %P2
 }
 
@@ -44,7 +44,7 @@ define fastcc i32 @test4(i32* %d) {
 ; CHECK: ret
 
 entry:
-  %tmp4 = load i32* %d
+  %tmp4 = load i32, i32* %d
   %tmp512 = lshr i32 %tmp4, 24
   ret i32 %tmp512
 }
@@ -62,8 +62,8 @@ entry:
   %i.zext = zext i16 %i to i32
   %index = lshr i32 %i.zext, 11
   %index.zext = zext i32 %index to i64
-  %val.ptr = getelementptr inbounds i32* %arr, i64 %index.zext
-  %val = load i32* %val.ptr
+  %val.ptr = getelementptr inbounds i32, i32* %arr, i64 %index.zext
+  %val = load i32, i32* %val.ptr
   %val.zext = zext i32 %val to i64
   %sum = add i64 %val.zext, %index.zext
   ret i64 %sum