CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / shl_undef.ll

diff --git a/test/CodeGen/X86/shl_undef.ll b/test/CodeGen/X86/shl_undef.ll
index 666c97281066c870d4cf9ce1a2fd47d17b974e3c..f59d014a2d85041f52f07a95a20d475a706867ca 100644 (file)
--- a/test/CodeGen/X86/shl_undef.ll
+++ b/test/CodeGen/X86/shl_undef.ll
@@ -4,7 +4,7 @@
 ; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after
 ; DAGCombiner optimization pass.  These are changed to undef and in turn
 ; the successor shl(s) become shl undef, 1.  This pattern then matches
-; shl x, 1 -> add x, x.  add undef, undef doesn't guarentee the low
+; shl x, 1 -> add x, x.  add undef, undef doesn't guarantee the low
 ; order bit is zero and is incorrect.
 ;
 ; See rdar://9453156 and rdar://9487392.
@@ -18,7 +18,7 @@ entry:
   %tmp0 = alloca i8
   %tmp1 = alloca i32
   store i8 1, i8* %tmp0
-  %tmp921.i7845 = load i8* %a0, align 1
+  %tmp921.i7845 = load i8, i8* %a0, align 1
   %tmp309 = xor i8 %tmp921.i7845, 104
   %tmp592 = zext i8 %tmp309 to i32
   %tmp862 = xor i32 1293461297, %tmp592
@@ -49,7 +49,7 @@ entry:
 ; shl undef, x -> 0
 define i32 @foo1_undef(i32* %a0) nounwind {
 entry:
-  %tmp1 = load i32* %a0, align 1
+  %tmp1 = load i32, i32* %a0, align 1
   %tmp2 = shl i32 undef, %tmp1;
   ret i32 %tmp2
 }