Turn on post-alloc scheduling for x86.

[oota-llvm.git] / test / CodeGen / X86 / sse2.ll

diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll
index 88e303d4a0072ed606ddabc19392ef616646e0e8..58fe28b09fe9a750177b3467120ca5a19b545dcf 100644 (file)
--- a/test/CodeGen/X86/sse2.ll
+++ b/test/CodeGen/X86/sse2.ll
@@ -1,6 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlpd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhpd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep movsd
+; Tests for SSE2 and below, without SSE3+.
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s
 
 define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
        %tmp3 = load <2 x double>* %A, align 16
@@ -8,6 +7,14 @@ define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
        %tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 2, i32 1 >
        store <2 x double> %tmp9, <2 x double>* %r, align 16
        ret void
+        
+; CHECK: t1:
+; CHECK:       movl    8(%esp), %eax
+; CHECK-NEXT:  movl    4(%esp), %ecx
+; CHECK-NEXT:  movapd  (%eax), %xmm0
+; CHECK-NEXT:  movlpd  12(%esp), %xmm0
+; CHECK-NEXT:  movapd  %xmm0, (%ecx)
+; CHECK-NEXT:  ret
 }
 
 define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
@@ -16,4 +23,12 @@ define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
        %tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 0, i32 2 >
        store <2 x double> %tmp9, <2 x double>* %r, align 16
        ret void
+        
+; CHECK: t2:
+; CHECK:       movl    8(%esp), %eax
+; CHECK-NEXT:  movl    4(%esp), %ecx
+; CHECK-NEXT:  movapd  (%eax), %xmm0
+; CHECK-NEXT:  movhpd  12(%esp), %xmm0
+; CHECK-NEXT:  movapd  %xmm0, (%ecx)
+; CHECK-NEXT:  ret
 }