-; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s -check-prefix=SSE -check-prefix=CHECK
-; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX -check-prefix=CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=AVX
; Test ADDSUB ISel patterns.
; }
define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test1:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test1:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%sub = fsub <4 x float> %A, %B
%add = fadd <4 x float> %A, %B
%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x float> %vecinit6
}
-; CHECK-LABEL: test1
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <8 x float> @test2(<8 x float> %A, <8 x float> %B) {
+; SSE-LABEL: test2:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm2, %xmm0
+; SSE-NEXT: addsubps %xmm3, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test2:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %ymm1, %ymm0, %ymm0
+; AVX-NEXT: retq
%sub = fsub <8 x float> %A, %B
%add = fadd <8 x float> %A, %B
%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x float> %vecinit14
}
-; CHECK-LABEL: test2
-; SSE: addsubps
-; SSE-NEXT: addsubps
-; AVX: vaddsubps
-; AVX-NOT: vaddsubps
-; CHECK: ret
-
define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
+; SSE-LABEL: test3:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd %xmm2, %xmm0
+; SSE-NEXT: addsubpd %xmm3, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test3:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT: retq
%sub = fsub <4 x double> %A, %B
%add = fadd <4 x double> %A, %B
%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x double> %vecinit6
}
-; CHECK-LABEL: test3
-; SSE: addsubpd
-; SSE: addsubpd
-; AVX: vaddsubpd
-; AVX-NOT: vaddsubpd
-; CHECK: ret
-
define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
+; SSE-LABEL: test4:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test4:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%add = fadd <2 x double> %A, %B
%sub = fsub <2 x double> %A, %B
%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
ret <2 x double> %vecinit2
}
-; CHECK-LABEL: test4
-; SSE: addsubpd
-; AVX: vaddsubpd
-; CHECK-NEXT: ret
-
define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
- %1 = load <4 x float>* %B
+; SSE-LABEL: test1b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test1b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps (%rdi), %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = load <4 x float>, <4 x float>* %B
%add = fadd <4 x float> %A, %1
%sub = fsub <4 x float> %A, %1
%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x float> %vecinit6
}
-; CHECK-LABEL: test1b
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
- %1 = load <8 x float>* %B
+; SSE-LABEL: test2b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps (%rdi), %xmm0
+; SSE-NEXT: addsubps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test2b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps (%rdi), %ymm0, %ymm0
+; AVX-NEXT: retq
+ %1 = load <8 x float>, <8 x float>* %B
%add = fadd <8 x float> %A, %1
%sub = fsub <8 x float> %A, %1
%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x float> %vecinit14
}
-; CHECK-LABEL: test2b
-; SSE: addsubps
-; SSE-NEXT: addsubps
-; AVX: vaddsubps
-; AVX-NOT: vaddsubps
-; CHECK: ret
-
define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
- %1 = load <4 x double>* %B
+; SSE-LABEL: test3b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd (%rdi), %xmm0
+; SSE-NEXT: addsubpd 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test3b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0
+; AVX-NEXT: retq
+ %1 = load <4 x double>, <4 x double>* %B
%add = fadd <4 x double> %A, %1
%sub = fsub <4 x double> %A, %1
%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x double> %vecinit6
}
-; CHECK-LABEL: test3b
-; SSE: addsubpd
-; SSE: addsubpd
-; AVX: vaddsubpd
-; AVX-NOT: vaddsubpd
-; CHECK: ret
-
define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
- %1 = load <2 x double>* %B
+; SSE-LABEL: test4b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test4b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = load <2 x double>, <2 x double>* %B
%sub = fsub <2 x double> %A, %1
%add = fadd <2 x double> %A, %1
%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
ret <2 x double> %vecinit2
}
-; CHECK-LABEL: test4b
-; SSE: addsubpd
-; AVX: vaddsubpd
-; CHECK-NEXT: ret
+define <4 x float> @test1c(<4 x float> %A, <4 x float>* %B) {
+; SSE-LABEL: test1c:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test1c:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps (%rdi), %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = load <4 x float>, <4 x float>* %B
+ %add = fadd <4 x float> %A, %1
+ %sub = fsub <4 x float> %A, %1
+ %vecinit6 = shufflevector <4 x float> %add, <4 x float> %sub, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
+ ret <4 x float> %vecinit6
+}
+
+define <8 x float> @test2c(<8 x float> %A, <8 x float>* %B) {
+; SSE-LABEL: test2c:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps (%rdi), %xmm0
+; SSE-NEXT: addsubps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test2c:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps (%rdi), %ymm0, %ymm0
+; AVX-NEXT: retq
+ %1 = load <8 x float>, <8 x float>* %B
+ %add = fadd <8 x float> %A, %1
+ %sub = fsub <8 x float> %A, %1
+ %vecinit14 = shufflevector <8 x float> %add, <8 x float> %sub, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
+ ret <8 x float> %vecinit14
+}
+
+define <4 x double> @test3c(<4 x double> %A, <4 x double>* %B) {
+; SSE-LABEL: test3c:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd (%rdi), %xmm0
+; SSE-NEXT: addsubpd 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test3c:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0
+; AVX-NEXT: retq
+ %1 = load <4 x double>, <4 x double>* %B
+ %add = fadd <4 x double> %A, %1
+ %sub = fsub <4 x double> %A, %1
+ %vecinit6 = shufflevector <4 x double> %add, <4 x double> %sub, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
+ ret <4 x double> %vecinit6
+}
+
+define <2 x double> @test4c(<2 x double> %A, <2 x double>* %B) {
+; SSE-LABEL: test4c:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test4c:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = load <2 x double>, <2 x double>* %B
+ %sub = fsub <2 x double> %A, %1
+ %add = fadd <2 x double> %A, %1
+ %vecinit2 = shufflevector <2 x double> %add, <2 x double> %sub, <2 x i32> <i32 2, i32 1>
+ ret <2 x double> %vecinit2
+}