Dont emit 'DBG_VALUE %noreg, ...' to terminate user variable ranges.

[oota-llvm.git] / test / CodeGen / X86 / sse3.ll

diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
index 8732579769af80e256eb2e2d4cdcb4af8b18a803..9a60091a0cf0e78bd6b028e784eff5cda03a5745 100644 (file)
--- a/test/CodeGen/X86/sse3.ll
+++ b/test/CodeGen/X86/sse3.ll
@@ -1,6 +1,6 @@
 ; These are tests for SSE3 codegen.  Yonah has SSE3 and earlier but not SSSE3+.
 
-; RUN: llvm-as < %s | llc -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\
+; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \
 ; RUN:              | FileCheck %s --check-prefix=X64
 
 ; Test for v8xi16 lowering where we extract the first element of the vector and
@@ -20,7 +20,7 @@ entry:
 ; X64:  pshuflw        $0, %xmm0, %xmm0
 ; X64: xorl    %eax, %eax
 ; X64: pinsrw  $0, %eax, %xmm0
-; X64: movaps  %xmm0, (%rdi)
+; X64: movdqa  %xmm0, (%rdi)
 ; X64: ret
 }
 
@@ -32,7 +32,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
         
 ; X64: t1:
 ; X64:         movl    (%rsi), %eax
-; X64:         movaps  (%rdi), %xmm0
+; X64:         movdqa  (%rdi), %xmm0
 ; X64:         pinsrw  $0, %eax, %xmm0
 ; X64:         ret
 }
@@ -66,7 +66,7 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
 ; X64:         pshufhw $100, %xmm0, %xmm1
 ; X64:         pinsrw  $1, %eax, %xmm1
 ; X64:         pextrw  $1, %xmm0, %eax
-; X64:         movaps  %xmm1, %xmm0
+; X64:         movdqa  %xmm1, %xmm0
 ; X64:         pinsrw  $4, %eax, %xmm0
 ; X64:         ret
 }
@@ -92,8 +92,8 @@ define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind {
        %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 >
        ret <8 x i16> %tmp
 ; X64:         t7:
-; X64:                 pshuflw $176, %xmm0, %xmm0
-; X64:                 pshufhw $200, %xmm0, %xmm0
+; X64:                 pshuflw $-80, %xmm0, %xmm0
+; X64:                 pshufhw $-56, %xmm0, %xmm0
 ; X64:                 ret
 }
 
@@ -120,9 +120,9 @@ define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind {
        store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res
        ret void
 ; X64:         t8:
-; X64:                 pshuflw $198, (%rsi), %xmm0
-; X64:                 pshufhw $198, %xmm0, %xmm0
-; X64:                 movaps  %xmm0, (%rdi)
+; X64:                 pshuflw $-58, (%rsi), %xmm0
+; X64:                 pshufhw $-58, %xmm0, %xmm0
+; X64:                 movdqa  %xmm0, (%rdi)
 ; X64:                 ret
 }
 
@@ -144,8 +144,9 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
        store <4 x float> %tmp13, <4 x float>* %r
        ret void
 ; X64:         t9:
-; X64:                 movsd   (%rsi), %xmm0
-; X64:                 movhps  %xmm0, (%rdi)
+; X64:                 movaps  (%rdi), %xmm0
+; X64:         movhps  (%rsi), %xmm0
+; X64:         movaps  %xmm0, (%rdi)
 ; X64:                 ret
 }
 
@@ -167,18 +168,12 @@ define internal void @t10() nounwind {
         store <4 x i16> %6, <4 x i16>* @g2, align 8
         ret void
 ; X64:         t10:
-; X64:                 movq    _g1@GOTPCREL(%rip), %rax
-; X64:                 movaps  (%rax), %xmm0
 ; X64:                 pextrw  $4, %xmm0, %eax
-; X64:                 movaps  %xmm0, %xmm1
-; X64:                 movlhps %xmm1, %xmm1
+; X64:                 unpcklpd %xmm1, %xmm1
 ; X64:                 pshuflw $8, %xmm1, %xmm1
 ; X64:                 pinsrw  $2, %eax, %xmm1
 ; X64:                 pextrw  $6, %xmm0, %eax
 ; X64:                 pinsrw  $3, %eax, %xmm1
-; X64:                 movq    _g2@GOTPCREL(%rip), %rax
-; X64:                 movq    %xmm1, (%rax)
-; X64:                 ret
 }
 
 
@@ -243,7 +238,7 @@ entry:
 ; X64:         t15:
 ; X64:                 pextrw  $7, %xmm0, %eax
 ; X64:                 punpcklqdq      %xmm1, %xmm0
-; X64:                 pshuflw $128, %xmm0, %xmm0
+; X64:                 pshuflw $-128, %xmm0, %xmm0
 ; X64:                 pinsrw  $2, %eax, %xmm0
 ; X64:                 ret
 }
@@ -256,18 +251,27 @@ entry:
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64:         t16:
-; X64:                 movaps  LCPI17_0(%rip), %xmm1
-; X64:                 movd    %xmm1, %eax
 ; X64:                 pinsrw  $0, %eax, %xmm1
 ; X64:                 pextrw  $8, %xmm0, %eax
 ; X64:                 pinsrw  $1, %eax, %xmm1
 ; X64:                 pextrw  $1, %xmm1, %ecx
 ; X64:                 movd    %xmm1, %edx
 ; X64:                 pinsrw  $0, %edx, %xmm1
-; X64:                 movzbl  %cl, %ecx
-; X64:                 andw    $65280, %ax
-; X64:                 orw     %cx, %ax
-; X64:                 movaps  %xmm1, %xmm0
 ; X64:                 pinsrw  $1, %eax, %xmm0
 ; X64:                 ret
 }
+
+; rdar://8520311
+define <4 x i32> @t17() nounwind {
+entry:
+; X64: t17:
+; X64:          movddup (%rax), %xmm0
+  %tmp1 = load <4 x float>* undef, align 16
+  %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+  %tmp3 = load <4 x float>* undef, align 16
+  %tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
+  %tmp5 = bitcast <4 x float> %tmp3 to <4 x i32>
+  %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
+  %tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0>
+  ret <4 x i32> %tmp7
+}