Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / store-narrow.ll

diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll
index 23aa616477876b382d11584ee45bf9e801eca970..0dd228eb145fe78184634a2021e3e7d9b8b7df58 100644 (file)
--- a/test/CodeGen/X86/store-narrow.ll
+++ b/test/CodeGen/X86/store-narrow.ll
@@ -1,5 +1,6 @@
 ; rdar://7860110
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
+; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.2"
 
@@ -12,8 +13,12 @@ entry:
   store i32 %D, i32* %a0, align 4
   ret void
   
-; CHECK: test1:
-; CHECK: movb  %sil, (%rdi)
+; X64: test1:
+; X64: movb    %sil, (%rdi)
+
+; X32: test1:
+; X32: movb    8(%esp), %al
+; X32: movb    %al, (%{{.*}})
 }
 
 define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
@@ -25,8 +30,12 @@ entry:
   %D = or i32 %B, %CS
   store i32 %D, i32* %a0, align 4
   ret void
-; CHECK: test2:
-; CHECK: movb  %sil, 1(%rdi)
+; X64: test2:
+; X64: movb    %sil, 1(%rdi)
+
+; X32: test2:
+; X32: movb    8(%esp), %al
+; X32: movb    %al, 1(%{{.*}})
 }
 
 define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
@@ -37,8 +46,12 @@ entry:
   %D = or i32 %B, %C
   store i32 %D, i32* %a0, align 4
   ret void
-; CHECK: test3:
-; CHECK: movw  %si, (%rdi)
+; X64: test3:
+; X64: movw    %si, (%rdi)
+
+; X32: test3:
+; X32: movw    8(%esp), %ax
+; X32: movw    %ax, (%{{.*}})
 }
 
 define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
@@ -50,8 +63,12 @@ entry:
   %D = or i32 %B, %CS
   store i32 %D, i32* %a0, align 4
   ret void
-; CHECK: test4:
-; CHECK: movw  %si, 2(%rdi)
+; X64: test4:
+; X64: movw    %si, 2(%rdi)
+
+; X32: test4:
+; X32: movl    8(%esp), %eax
+; X32: movw    %ax, 2(%{{.*}})
 }
 
 define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
@@ -63,8 +80,12 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret void
-; CHECK: test5:
-; CHECK: movw  %si, 2(%rdi)
+; X64: test5:
+; X64: movw    %si, 2(%rdi)
+
+; X32: test5:
+; X32: movzwl  8(%esp), %eax
+; X32: movw    %ax, 2(%{{.*}})
 }
 
 define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
@@ -76,6 +97,72 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret void
-; CHECK: test6:
-; CHECK: movb  %sil, 5(%rdi)
+; X64: test6:
+; X64: movb    %sil, 5(%rdi)
+
+
+; X32: test6:
+; X32: movb    8(%esp), %al
+; X32: movb    %al, 5(%{{.*}})
+}
+
+define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
+entry:
+  %OtherLoad = load i32 *%P2
+  %A = load i64* %a0, align 4
+  %B = and i64 %A, -280375465082881    ; 0xFFFF00FFFFFFFFFF
+  %C = zext i8 %a1 to i64
+  %CS = shl i64 %C, 40
+  %D = or i64 %B, %CS
+  store i64 %D, i64* %a0, align 4
+  ret i32 %OtherLoad
+; X64: test7:
+; X64: movb    %sil, 5(%rdi)
+
+
+; X32: test7:
+; X32: movb    8(%esp), %cl
+; X32: movb    %cl, 5(%{{.*}})
+}
+
+; PR7833
+
+@g_16 = internal global i32 -1
+
+; X64: test8:
+; X64-NEXT: movl _g_16(%rip), %eax
+; X64-NEXT: movl $0, _g_16(%rip)
+; X64-NEXT: orl  $1, %eax
+; X64-NEXT: movl %eax, _g_16(%rip)
+; X64-NEXT: ret
+define void @test8() nounwind {
+  %tmp = load i32* @g_16
+  store i32 0, i32* @g_16
+  %or = or i32 %tmp, 1
+  store i32 %or, i32* @g_16
+  ret void
+}
+
+; X64: test9:
+; X64-NEXT: orb $1, _g_16(%rip)
+; X64-NEXT: ret
+define void @test9() nounwind {
+  %tmp = load i32* @g_16
+  %or = or i32 %tmp, 1
+  store i32 %or, i32* @g_16
+  ret void
+}
+
+; rdar://8494845 + PR8244
+; X64: test10:
+; X64-NEXT: movsbl     (%rdi), %eax
+; X64-NEXT: shrl       $8, %eax
+; X64-NEXT: ret
+define i8 @test10(i8* %P) nounwind ssp {
+entry:
+  %tmp = load i8* %P, align 1
+  %conv = sext i8 %tmp to i32
+  %shr3 = lshr i32 %conv, 8
+  %conv2 = trunc i32 %shr3 to i8
+  ret i8 %conv2
 }