CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / store-narrow.ll

diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll
index e3cc2fa668efe07afb48f33baaccac55207895d9..6c1c56e43a4cf15ad9f803d385d41fd3e1b6a928 100644 (file)
--- a/test/CodeGen/X86/store-narrow.ll
+++ b/test/CodeGen/X86/store-narrow.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.2"
 
 define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -256     ; 0xFFFFFF00
   %C = zext i8 %a1 to i32
   %D = or i32 %C, %B
@@ -23,7 +23,7 @@ entry:
 
 define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -65281    ; 0xFFFF00FF
   %C = zext i8 %a1 to i32
   %CS = shl i32 %C, 8
@@ -40,7 +40,7 @@ entry:
 
 define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -65536    ; 0xFFFF0000
   %C = zext i16 %a1 to i32
   %D = or i32 %B, %C
@@ -56,7 +56,7 @@ entry:
 
 define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, 65535    ; 0x0000FFFF
   %C = zext i16 %a1 to i32
   %CS = shl i32 %C, 16
@@ -73,7 +73,7 @@ entry:
 
 define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i64* %a0, align 4
+  %A = load i64, i64* %a0, align 4
   %B = and i64 %A, -4294901761    ; 0xFFFFFFFF0000FFFF
   %C = zext i16 %a1 to i64
   %CS = shl i64 %C, 16
@@ -90,7 +90,7 @@ entry:
 
 define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i64* %a0, align 4
+  %A = load i64, i64* %a0, align 4
   %B = and i64 %A, -280375465082881    ; 0xFFFF00FFFFFFFFFF
   %C = zext i8 %a1 to i64
   %CS = shl i64 %C, 40
@@ -108,8 +108,8 @@ entry:
 
 define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
 entry:
-  %OtherLoad = load i32 *%P2
-  %A = load i64* %a0, align 4
+  %OtherLoad = load i32 , i32 *%P2
+  %A = load i64, i64* %a0, align 4
   %B = and i64 %A, -280375465082881    ; 0xFFFF00FFFFFFFFFF
   %C = zext i8 %a1 to i64
   %CS = shl i64 %C, 40
@@ -136,7 +136,7 @@ entry:
 ; X64-NEXT: movl %eax, _g_16(%rip)
 ; X64-NEXT: ret
 define void @test8() nounwind {
-  %tmp = load i32* @g_16
+  %tmp = load i32, i32* @g_16
   store i32 0, i32* @g_16
   %or = or i32 %tmp, 1
   store i32 %or, i32* @g_16
@@ -147,7 +147,7 @@ define void @test8() nounwind {
 ; X64-NEXT: orb $1, _g_16(%rip)
 ; X64-NEXT: ret
 define void @test9() nounwind {
-  %tmp = load i32* @g_16
+  %tmp = load i32, i32* @g_16
   %or = or i32 %tmp, 1
   store i32 %or, i32* @g_16
   ret void
@@ -160,7 +160,7 @@ define void @test9() nounwind {
 ; X64-NEXT: ret
 define i8 @test10(i8* %P) nounwind ssp {
 entry:
-  %tmp = load i8* %P, align 1
+  %tmp = load i8, i8* %P, align 1
   %conv = sext i8 %tmp to i32
   %shr3 = lshr i32 %conv, 8
   %conv2 = trunc i32 %shr3 to i8