CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / subreg-to-reg-1.ll

diff --git a/test/CodeGen/X86/subreg-to-reg-1.ll b/test/CodeGen/X86/subreg-to-reg-1.ll
index cf9f2d814253c9fbb2e2223e708b9df3ae18eb87..2931bab0cdd1a9bc0c1f782c0dea8499e25fb15c 100644 (file)
--- a/test/CodeGen/X86/subreg-to-reg-1.ll
+++ b/test/CodeGen/X86/subreg-to-reg-1.ll
@@ -1,11 +1,14 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal   .*), %e.\*} | count 1
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; CHECK:     {{leal    .*[)], %e.*}}
+; CHECK-NOT: {{leal    .*[)], %e.*}}
 
 ; Don't eliminate or coalesce away the explicit zero-extension!
 ; This is currently using an leal because of a 3-addressification detail,
 ; though this isn't necessary; The point of this test is to make sure
 ; a 32-bit add is used.
 
-define i64 @foo(i64 %a) {
+define i64 @foo(i64 %a) nounwind {
   %b = add i64 %a, 4294967295
   %c = and i64 %b, 4294967295
   %d = add i64 %c, 1