Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.

[oota-llvm.git] / test / CodeGen / X86 / subreg-to-reg-1.ll

diff --git a/test/CodeGen/X86/subreg-to-reg-1.ll b/test/CodeGen/X86/subreg-to-reg-1.ll
index 4e487e18472a5e63f8885548663e6eb59922c25b..4f31ab5a92291dabf1d786d7c4ebf207dccd9d65 100644 (file)
--- a/test/CodeGen/X86/subreg-to-reg-1.ll
+++ b/test/CodeGen/X86/subreg-to-reg-1.ll
@@ -1,8 +1,11 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movl   %e.\*, %e.\*} | count 1
+; RUN: llc < %s -march=x86-64 | grep "leal     .*), %e.*" | count 1
 
 ; Don't eliminate or coalesce away the explicit zero-extension!
+; This is currently using an leal because of a 3-addressification detail,
+; though this isn't necessary; The point of this test is to make sure
+; a 32-bit add is used.
 
-define i64 @foo(i64 %a) {
+define i64 @foo(i64 %a) nounwind {
   %b = add i64 %a, 4294967295
   %c = and i64 %b, 4294967295
   %d = add i64 %c, 1