-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
declare void @bar(i32)
declare void @car(i32)
ret void
}
-declare i8* @choose(i8*, i8*);
+declare i8* @choose(i8*, i8*)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
; CHECK: tail_duplicate_me:
; CHECK: movl $0, GHJK(%rip)
-; CHECK-NEXT: jmpq *%rbx
+; CHECK-NEXT: jmpq *%r
; CHECK: movl $0, GHJK(%rip)
-; CHECK-NEXT: jmpq *%rbx
+; CHECK-NEXT: jmpq *%r
; CHECK: movl $0, GHJK(%rip)
-; CHECK-NEXT: jmpq *%rbx
+; CHECK-NEXT: jmpq *%r
define void @tail_duplicate_me() nounwind {
entry:
; CHECK: dont_merge_oddly:
; CHECK-NOT: ret
-; CHECK: ucomiss %xmm0, %xmm1
-; CHECK-NEXT: jbe .LBB3_3
-; CHECK-NEXT: ucomiss %xmm2, %xmm0
-; CHECK-NEXT: ja .LBB3_4
-; CHECK-NEXT: .LBB3_2:
-; CHECK-NEXT: movb $1, %al
-; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB3_3:
-; CHECK-NEXT: ucomiss %xmm2, %xmm1
-; CHECK-NEXT: jbe .LBB3_2
-; CHECK-NEXT: .LBB3_4:
+; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
+; CHECK-NEXT: jbe .LBB2_3
+; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
+; CHECK-NEXT: ja .LBB2_4
+; CHECK-NEXT: jmp .LBB2_2
+; CHECK-NEXT: .LBB2_3:
+; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
+; CHECK-NEXT: jbe .LBB2_2
+; CHECK-NEXT: .LBB2_4:
; CHECK-NEXT: xorb %al, %al
; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: ret
define i1 @dont_merge_oddly(float* %result) nounwind {
entry:
; an unconditional jump to complete a two-way conditional branch.
; CHECK: c_expand_expr_stmt:
-; CHECK: jmp .LBB4_7
-; CHECK-NEXT: .LBB4_12:
-; CHECK-NEXT: movq 8(%rax), %rax
-; CHECK-NEXT: movb 16(%rax), %al
-; CHECK-NEXT: cmpb $16, %al
-; CHECK-NEXT: je .LBB4_6
-; CHECK-NEXT: cmpb $23, %al
-; CHECK-NEXT: je .LBB4_6
-; CHECK-NEXT: jmp .LBB4_15
-; CHECK-NEXT: .LBB4_14:
-; CHECK-NEXT: cmpb $23, %bl
-; CHECK-NEXT: jne .LBB4_15
-; CHECK-NEXT: .LBB4_15:
+;
+; This test only works when register allocation happens to use %rax for both
+; load addresses.
+;
+; CHE: jmp .LBB3_11
+; CHE-NEXT: .LBB3_9:
+; CHE-NEXT: movq 8(%rax), %rax
+; CHE-NEXT: xorb %dl, %dl
+; CHE-NEXT: movb 16(%rax), %al
+; CHE-NEXT: cmpb $16, %al
+; CHE-NEXT: je .LBB3_11
+; CHE-NEXT: cmpb $23, %al
+; CHE-NEXT: jne .LBB3_14
+; CHE-NEXT: .LBB3_11:
%0 = type { %struct.rtx_def* }
%struct.lang_decl = type opaque
declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly
declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
+
+
+; If one tail merging candidate falls through into the other,
+; tail merging is likely profitable regardless of how few
+; instructions are involved. This function should have only
+; one ret instruction.
+
+; CHECK: foo:
+; CHECK: callq func
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: popq
+; CHECK-NEXT: ret
+
+define void @foo(i1* %V) nounwind {
+entry:
+ %t0 = icmp eq i1* %V, null
+ br i1 %t0, label %return, label %bb
+
+bb:
+ call void @func()
+ ret void
+
+return:
+ ret void
+}
+
+declare void @func()
+
+; one - One instruction may be tail-duplicated even with optsize.
+
+; CHECK: one:
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $0, XYZ(%rip)
+
+@XYZ = external global i32
+
+define void @one() nounwind optsize {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ store volatile i32 0, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ store volatile i32 0, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; two - Same as one, but with two instructions in the common
+; tail instead of one. This is too much to be merged, given
+; the optsize attribute.
+
+; CHECK: two:
+; CHECK-NOT: XYZ
+; CHECK: ret
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+; CHECK-NOT: XYZ
+
+define void @two() nounwind optsize {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; two_nosize - Same as two, but without the optsize attribute.
+; Now two instructions are enough to be tail-duplicated.
+
+; CHECK: two_nosize:
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+
+define void @two_nosize() nounwind {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; Tail-merging should merge the two ret instructions since one side
+; can fall-through into the ret and the other side has to branch anyway.
+
+; CHECK: TESTE:
+; CHECK: ret
+; CHECK-NOT: ret
+; CHECK: size TESTE
+
+define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
+entry:
+ %cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1]
+ %varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1]
+ %cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1]
+ br i1 %cmp410, label %for.end, label %bb.nph
+
+bb.nph: ; preds = %entry
+ %tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1]
+ ret i64 %tmp15
+
+for.end: ; preds = %entry
+ ret i64 %varx.0
+}
projects / oota-llvm.git / blobdiff