; CHECK: tail_duplicate_me:
; CHECK: movl $0, GHJK(%rip)
-; CHECK-NEXT: jmpq *%rbx
+; CHECK-NEXT: jmpq *%r
; CHECK: movl $0, GHJK(%rip)
-; CHECK-NEXT: jmpq *%rbx
+; CHECK-NEXT: jmpq *%r
; CHECK: movl $0, GHJK(%rip)
-; CHECK-NEXT: jmpq *%rbx
+; CHECK-NEXT: jmpq *%r
define void @tail_duplicate_me() nounwind {
entry:
; CHECK: dont_merge_oddly:
; CHECK-NOT: ret
-; CHECK: ucomiss %xmm1, %xmm2
+; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: jbe .LBB2_3
-; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: ja .LBB2_4
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_3:
-; CHECK-NEXT: ucomiss %xmm0, %xmm2
+; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: jbe .LBB2_2
; CHECK-NEXT: .LBB2_4:
; CHECK-NEXT: xorb %al, %al
; an unconditional jump to complete a two-way conditional branch.
; CHECK: c_expand_expr_stmt:
-; CHECK: jmp .LBB3_7
-; CHECK-NEXT: .LBB3_12:
-; CHECK-NEXT: movq 8(%rax), %rax
-; CHECK-NEXT: movb 16(%rax), %al
-; CHECK-NEXT: cmpb $16, %al
-; CHECK-NEXT: je .LBB3_6
-; CHECK-NEXT: cmpb $23, %al
-; CHECK-NEXT: je .LBB3_6
-; CHECK-NEXT: jmp .LBB3_15
-; CHECK-NEXT: .LBB3_14:
-; CHECK-NEXT: cmpb $23, %bl
-; CHECK-NEXT: jne .LBB3_15
-; CHECK-NEXT: .LBB3_15:
+;
+; This test only works when register allocation happens to use %rax for both
+; load addresses.
+;
+; CHE: jmp .LBB3_11
+; CHE-NEXT: .LBB3_9:
+; CHE-NEXT: movq 8(%rax), %rax
+; CHE-NEXT: xorb %dl, %dl
+; CHE-NEXT: movb 16(%rax), %al
+; CHE-NEXT: cmpb $16, %al
+; CHE-NEXT: je .LBB3_11
+; CHE-NEXT: cmpb $23, %al
+; CHE-NEXT: jne .LBB3_14
+; CHE-NEXT: .LBB3_11:
%0 = type { %struct.rtx_def* }
%struct.lang_decl = type opaque
; CHECK: foo:
; CHECK: callq func
; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: addq $8, %rsp
+; CHECK-NEXT: popq
; CHECK-NEXT: ret
define void @foo(i1* %V) nounwind {
]
bb7:
- volatile store i32 0, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
unreachable
bbx:
]
bb12:
- volatile store i32 0, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
unreachable
return:
]
bb7:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
bbx:
]
bb12:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
return:
]
bb7:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
bbx:
]
bb12:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
return:
ret void
}
+
+; Tail-merging should merge the two ret instructions since one side
+; can fall-through into the ret and the other side has to branch anyway.
+
+; CHECK: TESTE:
+; CHECK: ret
+; CHECK-NOT: ret
+; CHECK: size TESTE
+
+define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
+entry:
+ %cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1]
+ %varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1]
+ %cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1]
+ br i1 %cmp410, label %for.end, label %bb.nph
+
+bb.nph: ; preds = %entry
+ %tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1]
+ ret i64 %tmp15
+
+for.end: ; preds = %entry
+ ret i64 %varx.0
+}