This commit enables unaligned memory accesses of vector types on AArch64 back end...

[oota-llvm.git] / test / CodeGen / X86 / tailcall-cgp-dup.ll

diff --git a/test/CodeGen/X86/tailcall-cgp-dup.ll b/test/CodeGen/X86/tailcall-cgp-dup.ll
index 10fe146fd67f6227e9fed2810c3da5817d46c868..a51bc889924b47a6ec91b15cc829ecc6c320b33e 100644 (file)
--- a/test/CodeGen/X86/tailcall-cgp-dup.ll
+++ b/test/CodeGen/X86/tailcall-cgp-dup.ll
@@ -4,7 +4,7 @@
 ; rdar://9147433
 
 define i32 @foo(i32 %x) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   switch i32 %x, label %return [
     i32 1, label %sw.bb
@@ -61,3 +61,27 @@ declare i32 @f4()
 declare i32 @f5()
 
 declare i32 @f6()
+
+; rdar://11958338
+%0 = type opaque
+
+declare i8* @bar(i8*) uwtable optsize noinline ssp
+
+define hidden %0* @thingWithValue(i8* %self) uwtable ssp {
+entry:
+; CHECK-LABEL: thingWithValue:
+; CHECK: jmp _bar
+  br i1 undef, label %if.then.i, label %if.else.i
+
+if.then.i:                                        ; preds = %entry
+  br label %someThingWithValue.exit
+
+if.else.i:                                        ; preds = %entry
+  %call4.i = tail call i8* @bar(i8* undef) optsize
+  br label %someThingWithValue.exit
+
+someThingWithValue.exit:                          ; preds = %if.else.i, %if.then.i
+  %retval.0.in.i = phi i8* [ undef, %if.then.i ], [ %call4.i, %if.else.i ]
+  %retval.0.i = bitcast i8* %retval.0.in.i to %0*
+  ret %0* %retval.0.i
+}