CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / tailcallbyval64.ll

diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll
index 1b1efe713c6e3cc5cf803ae99c4c823934c87830..9df1470c67f13fceadbd9ad8242c111c19b94fa3 100644 (file)
--- a/test/CodeGen/X86/tailcallbyval64.ll
+++ b/test/CodeGen/X86/tailcallbyval64.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -mtriple=x86_64-linux  -tailcallopt  | FileCheck %s
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux  -tailcallopt  | FileCheck %s
 
 ; FIXME: Win64 does not support byval.
 
 ; Expect the entry point.
-; CHECK: tailcaller:
+; CHECK-LABEL: tailcaller:
 
 ; Expect 2 rep;movs because of tail call byval lowering.
 ; CHECK: rep;
@@ -35,8 +35,8 @@ declare  fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %v
 
 define  fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) {
 entry:
-        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
-        %tmp3 = load i64* %tmp2, align 8
-        %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* %a byval, i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
+        %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1
+        %tmp3 = load i64, i64* %tmp2, align 8
+        %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
         ret i64 %tmp4
 }